CHAPTER 4: 555 TIMER

555 Timer : Pin Functions • PIN 1: Ground - usually connected to ground. The voltage should be the most negative of any voltage appearing at the other...

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CHAPTER 4: 555 TIMER

Dr. Wan Mahani Hafizah binti Wan Mahmud

555 TIMER • • • • • •

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Introduction Pin configuration Basic architecture and operation Astable Operation Monostable Operation Timer in Triggering Circuits

555 Timer – Introduction

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• 555 Timer is a highly stable & inexpensive device for generating accurate time delay or oscillation • It can provide time delays ranging from microseconds to hours • It can be used with power supply voltage ranging from +3V to +18V • It can source or sink up to 200mA • It is compatible with both TTL & CMOS logic circuits • It has very high temperature stability & it is designed to operate in the temperature range -55° to +125°C

555 Timer : Application • The 555 integrated circuit has been around for more than two decades, but continues to be popular in electronic design • It is a versatile device that can perform as a timer, time-delay circuit, oscillator, voltage-controlled oscillator, and many other functions • Applications examples: – Waveform generators – Burglar Alarms – Measurement, Process & Control Circuits – Missing pulse detectors – Traffic light control – Automatic Battery chargers – Logic probes – DC to DC Converters

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555 Timer - IC Configuration First introduced in 1971 by Signetics Corporation and it was called “The IC Time Machine”. Designed and invented by Hans R. Camenzind. Comes in 2 packages, either the round metal-can called the ‘T’ package and the more familiar 8-pin DIP ‘V’ package. There is also 14 pins version. Has eight connections (called pins) to its plastic case, arranged as four on one side and four on the other, as shown in the following pin-out.

5

Fig. 4.21

The 555 Timer – A Black Box! 1

8

2

7 555

3

6

4

5

• Eight connections called ‘pins’ • Little white dot and dimple denote pin 1

555 Timer : Pin Functions • PIN 1 : Ground - usually connected to ground. The voltage should be the most negative of any voltage appearing at the other pins. • PIN 2 : Trigger - level-sensitive point to 1/3 VCC. When the voltage at this pin is brought below 1/3 VCC the flip-flop is set causing pin 3 to produce a high state. Allowable applied voltage is between VCC (pin 8) and ground (pin 1). • PIN 3 : Output – level here is normally low and goes high during the timing interval. Since the output stage is active in both directions, it can source or sink up 200 mA.

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555 Timer : Pin Functions (cont.)  PIN 4 : Reset - when voltage at this pin is less than 0.4 V, the timing cycle is interrupted returning the timer to its non-triggered state. This is an overriding function so that the timer cannot be triggered unless reset is released (pin 4 > 1.0 V). When not used, connect to VCC.  PIN 5 : Control Voltage - internally derived 2/3 VCC point. A resistor-to-ground or an external voltage may be connected to pin 5 to change the comparator reference points. When not used for this purpose, a capacitor-toground greater than or equal to 0.01 mF is recommended for all applications.  PIN 6 : Threshold – level sensitive point to 2/3 VCC. When the voltage at this pin is brought greater than 2/3 VCC, the flip-flop is reset causing pin 3 to produce a low state. 8

555 Timer : Pin Functions (cont.)  PIN 7 : Discharge - collector of a transistor switch to ground (pin 1). It is normally used to discharge the timing capacitor.  PIN 8 : Power Supply - the power-supply voltage (VCC) connected here can range from 4.5 to 18 V with respect to ground (pin 1). This depends on the manufacturer specification. The common value is 5V DC when working with digital ICs. The supply current between 3 to 6mA and a Rise/Fall time of 100ns.

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Internal Circuitry - Example

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Manufacturer : Philips Semiconductors

Timer Architecture : Block Diagram • Fig. 4.22: Timer architecture

11

Different Internal Block Diagram

Different manufacturer will have different architecture (internal structure, circuitry and block diagram) 12

555 Timer – Mode of Operation • The 555 timer has essentially two modes of operation: – Astable multivibrator (free running) – no stable state (never stable) : generating continuous train of pulses and – Monostable multivibrator (one shot) – one stable state Gnd 1 Trigger 2 Output 3 13

Reset 4

8 +Vcc 555 Timer

7 Discharge 6 Threshold 5 Control voltage

Astable Multivibrator • The frequency of output is determined by the external components R1, R2, and C1 • The output at pin 3 is a square-wave • The frequency of output or called frequency of oscillation is given by this equation: C2

1.44 f = (R1 + 2 R2 )C1

C1

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Astable – Circuit Operation +VCC R1

8

4

7

off Pin 6 0V 6

R2

R

V- > V+

2VCC/3 CA

5

C2

R=‘0’

R

S=‘1’

VCC/3

C1 initially C1 uncharged (VC1 = 0) 15

Pin 2 0V

CB

2

R 1

V+ > V-

R Q S

Q

Vref Q=‘0’ Q=‘1’

3

VO

VCC 0

Astable – Circuit Operation (cont.) +VCC R1

8

4

7

on R

6

R2

5

2VCC/3

R VCC/3

2VCC/3

0 16

R=‘1’ S=‘0’ S CB

2

R C1

CA R Q

C2 VCC

V+ > V-

1

V- > V+

Q

Vref Q=‘1’ 3

Q=‘0’

VO

VCC 0

Astable – Circuit Operation (cont.) +VCC R1

8

4

7

off R 6

R2

2VCC/3

5

C2

V- > V+

CA R=‘0’

R

S=‘1’ S

VCC/3

CB

2

2VCC/3

R C1

0 17

VCC/3

1

R Q

V+ > V-

Q

Vref Q=‘0’ Q=‘1’

VCC 3 VO 0

Astable – Circuit Operation (cont.) •







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When power is first applied to the circuit, the capacitor will be uncharged therefore, both the trigger (Pin 2) and threshold (Pin 6) inputs will be near zero volts. The lower comparator (CB) sets the control flip-flop causing the output (Pin 3) to switch HIGH. That also turns off internal transistor Q1. That allows the capacitor to begin charging through R1 and R2 towards the supply voltage (VCC). As soon as the charge on the capacitor reaches 2/3 of the supply voltage, the upper comparator (CA) will trigger causing the flip-flop to reset. That causes the output to switch LOW. Internal transistor Q1 also conducts (ON). The effect of Q1 conducting causes capacitor C1 to be connected to ground through resistor R2, and Q1. The result of that is that the capacitor now begins to discharge with current flowing through R2 into the discharge pin (Pin 7). As soon as the voltage across the capacitor reaches 1/3 of the supply voltage, the lower comparator is triggered. That again causes the control flip-flop to set and the output to go HIGH. Transistor Q1 cuts off and the discharge pin is disconnected, allowing the capacitor to charge again. That cycle continues to repeat with the capacitor alternately charging and discharging, as the comparators cause the flip-flop to be repeatedly set and reset. The resulting output is a continuous stream of rectangular pulses unless the Reset input connected to 0V which causes the output LOW while Reset is 0V.

Astable : Output waveform thigh = tH = tmark = tm

tlow= tL = tspace = tS

VCC Vo 0V

2VCC/3 Vc VCC/3 0 19

t1

t2

Finding Time and Frequency of Oscillation • The principle used : the timing of capacitor being charged and discharged (remember relaxation oscillator) • The basic equation used: −t  vc (t ) = vc (0) + (vc (∞) − vc (0) )1 − e τ   

= vc (∞) + (vc (0) − vc (∞) ) e

−t

τ

where vc(0) : the initial value of capacitor voltage vc(∞) : the steady state value of the capacitor voltage

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Time ‘High’ – Capacitor charging • Use: vc (t1 ) = vc ( ∞ ) + (vc (0) − vc ( ∞ ) )e • From graph: VC(t1) = 2VCC/3 VC(∞) = VCC

VC(0) = VCC/3

2VCC  VCC  = VCC +  − VCC   e 3  3  V  2V − CC =  − CC 3 3  − t1

1 = 2e t1 21

e

τ1

=2

τ1

− t1

  − t1 τ 1     e  



− t1

e

τ1

τ1

  

− t1

τ1

vC VCC 2VCC/3 τ1 =(R1+R2)C1 VCC/3

=

1 2

⇒ t1 = τ 1 ln 2

0

t1

t1 = 0.693 (R1 + R2 )C1

t

Time ‘Low’ – Capacitor discharging • Use: vc (t2 ) = vc ( ∞) + (vc (0) − vc ( ∞ ) )e VC(t2) = VCC/3 VC(∞) = 0

VC(0) = 2VCC/3

VCC  2VCC   −t2 τ 2   = 0+ − 0   e 3  3   VCC  2VCC   −t 2 τ 2   =   e 3  3   1 = 2e 22

τ2

vC

• From graph:

−t2

− t2

VCC 2VCC/3

τ2= R2C1 VCC/3 0

τ2

t 2 = τ 2 ln 2



t2 = 0.693 R2 C1

t2

t

Time and Frequency of Oscillation • Time:

T

= t1 + t2 = 0.693 (R1 + R2 )C1 + 0.693 R2 C1

T

= 0.693 (R1 + 2 R2 )C1

Frequency: f

f 23

1 = T =

=

1 0.693 (R1 + 2 R2 )C1

1.44 (R1 + 2 R2 )C1

Astable : Duty Cycle t high

t1 t1 = = D= t high + tlow t1 + t 2 T 0.693 (R1 + R2 )C1 = 0.693 (R1 + 2 R2 )C1 R + R2 D= 1 R1 + 2R2

• The formula:

• Usually it is expressed in %:

D=

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thigh thigh + tlow

t1 = thigh = tmark t2 = tlow = tspace

× 100 % =

thigh T

× 100 %

Duty Cycle - Example

Fig. 4.26 25

Exercise: Determine fo and duty cycle •

Frequency of oscillation:

f = =

1.44 (R1 + 2 R2 )Cext 1.44 (2.2k + 9.4k )(0.022µ )

= 5.64 kHz •

Duty Cycle:

D=

R1 + R2 (R1 + 2 R2 )

2.2k + 4.7k x 100% (2.2k + 2(4.7k ) ) = 59.5 % =

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Astable - Exercise +VCC R1 R2

4 7 2 6

C1

8 3 555 1

V0

5

• Compute R1 and R2 to generate a pulse of 120 beats/minute • Given C1 = 47µF • TON = 60% T

C2

T = TON + TOFF TON = 0.693( R1 + R2 )C

TOFF = 0.693( R2 )C 27

Astable – Exercise : Solution Time period of one beat, T =

TON = 60%T =

60 60 = = 0 .5 Number of beats per minute 120

60 × 0.5 = 0.3sec 100

TOFF = 40%T =

40 × 0.5 = 0.2 sec 100

TOFF = 0.693 × R2 × C

TON = 0.693 × ( R1 + R2 ) × C

0.2 = 0.693 × R2 × 47 ×10−6

0.3 = 0.693 × ( R1 + 6140.43) × 47 × 10 −6

0 .2 0.693 × 47 ×10 −6 = 6140.43 Ω

R2 =

0.3 − 6140.43 0.693 × 47 ×10 −6 = 3070.21Ω

R1 =

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Monostable Multivibrator +VCC

R1

4

8

7 Trigger Input

2 6

3

555

1

C1

5 C2

Fig. 4.10 29

Vo

The monostable circuit generates a single pulse of fixed time duration each time it receives an input trigger pulse, thus it is named one-shot

Monostable Multivibrator (cont.) • Monostable multivibrator is used to turn circuit or external component ON or OFF for a specific length of time. It is also used to generate delays. • When multiple one-shots are cascaded, a variety of sequential timing pulses can be generated. Those pulses will allow to time and sequence a number of related operations. • It is called a monostable because it is stable in just one state: 'output low'. The 'output high' state is temporary or unstable. • If there is no triggering input, the circuit stays in its stable condition which is the OFF-state. The output stays at zero. • Whenever it is triggered by an input pulse, the monostable switches to its temporary state. • It remains in that state for a period of time determined by an R1 and C1 network. It then returns to its stable state. 30

Monostable – Circuit Operation +VCC R1

8

4

7

on

C1 initially uncharged C1 (VC1 = 0) C1 remain uncharged And no trigger voltage is applied

R

Pin 6 0V 6

2VCC/3

5

C2

R

V- > V+

CA R=‘0’

S=‘0’ S

VCC/3

VT

CB

2

>VCC/3

Note: VT must < VCC/3 to trigger comparator CB 31output to high

R 1

R Q

V- > V+

Q

Vref Q=‘1’ 3

Q=‘0’

VO 0 Stable state

Monostable – Circuit Operation +VCC R1

8

4

7

on off

CC11 initially now uncharged is being C1 (VC1 = 0) charged

R

Pin 6 0V 6

2VCC/3

5

C2 Now trigger voltage is applied VT VCC32 /3

0

R

V- > V+

CA R=‘0’

S=‘1’ S

VCC/3

VT

CB

2


R 1

R Q

V+ > V-

Q

Vref Q=‘0’ Q=‘1’ 3

Q=‘1’ Q=‘0’

VO

VCC

0 Stable state

vC

Monostable – Circuit Operation

VCC

+VCC

2VCC/3

R1

8

4

7

on off

τ =R1C1

R

C1 6

0

t

2VCC/3 CA

5

T

C2

R VCC/3

VT high VT VCC33 /3

0

V+ > V-

R=‘1’

R Q

S=‘0’ S

CB

2

R 1

V-

>

V+

Q

Vref Q=‘0’ Q=‘1’

T 3

Q=‘0’ Q=‘1’

VO 0 unstable state

Operation Concept •







34

The timing period is triggered (started) when the Trigger input (pin 2) is less than 1/3 VCC, this makes the Output HIGH (VCC) and the capacitor C1 starts to charge through resistor R1. Once the time period has started further trigger pulses are ignored. The Threshold input (pin 6) monitors the voltage across C1 and when this reaches 2/3 VCC, the time period is over and the Output becomes LOW. At the same time the Discharge (pin 7) is connected to 0V, discharging the capacitor and ready for the next trigger. The Reset input (pin 4) will overrides all other inputs and the timing may be cancelled at any time by connecting Reset pin to 0V, this instantly makes the output low and discharges the capacitor. Therefore, if the Reset function is not required then the reset pin should be connected to +VCC. If the trigger input is still less than 1/3 Vs at the end of the time period the output will remain high until the trigger is greater than 1/3 VCC. This situation can occur if the input signal is from an on-off switch or sensor.

Waveforms Relationship

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Output Waveform

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Fig. 4.11

Time Period • The time at the unstable state is the time period or time at ‘High state’: T = 1.1 R1 C1 where: T = time period in seconds (s) R1 = resistance in ohms (Ω) C1 = capacitance in farads (F)

• This equation arises from the time it takes the exponential RC transient to reach the resetting voltage of 2/3 of the supply

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Time ‘High’ – Capacitor charging vc (T ) = vc ( ∞) + (vc (0) − vc ( ∞) )e

• Use: • From graph:

VC(T) = 2VCC/3 VC(∞) = VCC

e 38

τ

=3

τ

vC

VC(0) = 0

VCC 2VCC/3

−T 2VCC  = VCC + (0 − VCC ) e τ    3 −T VCC  − = (− VCC ) e τ    3 −T 1 =e τ 3 T

−T

⇒ T = τ ln 3

τ =R1C1 0

T = 1.1 R1 C1

T

t

Edge-Triggering • The monostable can be made edge triggered, responding only to changes of an input signal, by connecting the trigger signal through a capacitor to the trigger input • The capacitor passes sudden changes (AC) but blocks a constant (DC) signal. The circuit is 'negative edge triggered' because it responds to a sudden fall in the input signal • The resistor between the trigger (pin 2) and Vs ensures that the trigger is normally high (Vs)

Fig. 4.12 39

555 timer : Pulse-width modulation (PWM) • When the 555 timer is connected in the monostable mode, an external signal applied to the control voltage terminal will change the charging time of the timing capacitor and the pulse width • If the one-shot is triggered with a continuous pulse train, the output pulse width will be modulated by the external signal. This circuit is known as a pulse width modulator (PWM) • In PWM, a low-frequency signal called a modulating signal is capacitively coupled into pin 5. This signal could be a voice or computer data • Since pin 5 controls the value of UTP, Vmod is being added to the quiescent UTP. This means that the instantaneous UTP varies sinusoidally between ±Vmod

 2VCC  UTP =  + Vmod   3  40

Where: Vmod is the peak value of the modulating signal

555 timer : Pulse-width modulation (PWM) (cont.) +VCC 8

The output frequency is established by the input clock T

4 3

R 7

555 6 C

5 2

Clock in 41

T

1

PWM out

f=1/T

W A B

Modulating signal in

 2VCC  + Vmod  UTP =   3   UTP   W = − RC ln1 − VCC  

555 timer : Pulse-width modulation (PWM) (cont.) • A train of triggers called the clock is the input to pin 2. Each trigger produces an output pulse • Since the period of the triggers is T, the output will be a series of rectangular pulse with a period of T • The modulating signal has no effect on the period T, but it does change the width of each output pulse

 UTP   W = − RC ln 1 − VCC   42

T PWM out

W A

Modulating signal

B

At point A, the positive peak of the modulating signal, the output pulse is wide. At point B, the negative peak of the modulating signal, the output pulse is narrow

555 timer : Pulse-width modulation (PWM) (cont.) • With PWM the pulse width changes, but the period is constant because it is determined by the frequency of the input triggers • Because the period is fixed, the position of each pulse is the same, which means that the leading edge of the pulse always occurs after a fixed interval of time • PWM is widely used in communication. It allows a lowfrequency modulating signal (voice or data) to change the pulse width of a high-frequency signal called the carrier. The modulated carrier then can be transmitted

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PWM Application : Speed Controller 12V Vs

R3 1kΩ

R5 33kΩ

8

LM555CM Timer

VCC

Q1

2N3906

4

RST

7

DIS

6

THR

2

TRI

5

CON

R4 2.2kΩ

OUT

3

12V Vs

GND 1

100nF C

Ramp

100nF Cf R3 1kΩ

R1 10kΩ

12V Vs R5 33kΩ

8

LM555CM Timer

VCC

Q1

2N3906

4

RST

7

DIS

6

THR

2

TRI

5

CON

R4 2.2kΩ

OUT

R6 10kΩ 10% Key=A

3

12V Vs

R2 10kΩ

5

1

100nF C

100nF Cf

PWMout 7

Ramp 6 4

44

R7 1kΩ

8

GND

U1B TLC393MJG

555 timer : Pulse-position modulation (PPM) • For PPM, the 555 timer is in astable mode. The PPM circuit configuration is quite similar to VCO • Just like PWM, the modulating signal is coupled into pin 5 (the control voltage terminal) • The modulating signal will vary the instantaneous UTP:

 2VCC  UTP =  + Vmod   3 

where: Vmod is the peak value of the modulating signal

• When the modulating signal increases, UTP increases and the pulse width increases too. But when the modulating signal decreases, UTP decreases and the pulse width decreases. • The result is the pulse width (time high) will be varied

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555 timer : Pulse-position modulation (PPM) (cont.) R1

+VCC 8

Pulse width is variable

4

PPM output

3

7

555

R2

Space is constant

C 6

5 2

46

The leading edge of each pulse is a function of the modulation.

1

A B

Modulating signal in

555 timer : Pulse-position modulation (PPM) (cont.) T = W + 0.693R2C

• The output period:

• The pulse width (W = tH):

 V − UTP   W = −(R1 + R2 )C ln CC  VCC − 0.5UTP  • The space width (S = tL):

S = 0.693R2C

– The space is the time between the trailing edge of one pulse and the leading edge of the next pulse – The space between pulses is constant

47

555 timer : Pulse-position modulation (PPM) (cont.) • Since the space is constant, the position of the leading edge of any pulse depends on how wide the preceding pulse is

W

Pulse width is variable PPM output

Space is constant • Both the width (W)Tand the period (T) of pulses vary with modulating signal • Like PWM, PPM is used in communication systems to transfer voice or data 48

555 timer : Ramp Generator • A linear ramp generator can be constructed using 555 timer in monostable mode • The normal charging, pattern of the timing capacitor is exponential because of the RC circuit • If resistor R is replaced by a constant current source, a linear ramp will be generated • The resistor R in monostable configuration is replaced with a pnp current source that produces a constant charging current:

VCC − VE RE • When a trigger pulse (VT) is applied at pin 2, the pnp current source forces a constant charging current into the capacitor. Therefore the voltage across the capacitor is a ramp IC =

49

555 timer : Ramp Generator (cont.) +VCC R1

RE VE

VE = VB + VBE

VB 4

VT

8

2

R2

VCC − VE IC = RE

IC

7

 R2   VB = VCC   R1 + R2 

555

Vo

6

5 1

0.01µF

S

C 0V

T 50

V

555 timer : Ramp Generator (cont.)

Trigger Voltage: VT

0V

S Output Voltage:

0V T

T : Duration of the ramp

2VCC T= 3S 51

V : Peak value of the ramp

2VCC V= 3 S : Slope of the ramp

IC S= C

Q&A

52