COURSE OUTLINE Department & Faculty: Electrical Engineering Faculty Course Code: SKEE 2263 Digital Systems Total Contact Hours: 42 hours
Page : 1 of 4
Semester: 1 Academic Session: 2016/2017
PM MUHAMMAD MUN’IM BIN AHMAD ZABIDI (
[email protected])
Course Coordinator
:
Section
Program
Lecturer
Contact Info
1
SKEE
Muhammad Nadzir Marsono
[email protected]
Synopsis
:
This course is a continuation from basic digital logic techniques course SKEE 1223 Digital Electronics. The objective of the course is to introduce students to basic techniques to design and implement complex digital systems. It emphasizes on techniques to design, analyze, plan, and implement complex digital systems using programmable logic. In order to facilitate learning process, computer-aided design (CAD) software is used throughout the course. Actual environment problems and solutions are provided.
LEARNING OUTCOMES At the end of the course, students should be able to: Programme Outcome
Taxonomies and Soft-Skills
Assessment Methods
Analyze and construct complex digital systems within defined specifications using CAD tools.
PO5
C6
T, F
CO2
Identify and select appropriate references and components as design resources.
PO8
LL1
A, F
CO3
Design complex digital systems responsibly and ethically.
PO11
EM1
A
No.
Course Learning Outcome
CO1
(T – Test ; A – Assignment; F – Final Exam)
Prepared by: Name: PM Muhammad Mun’im bin Ahmad Zabidi Signature: Date: 14 February, 2016
Certified by: (Course Panel Head) Name: Signature: Date:
COURSE OUTLINE Department & Faculty: Electrical Engineering Faculty Course Code: SKEE 2263 Digital Systems Total Contact Hours: 42 hours
Page : 2 of 4
Semester: 1 Academic Session: 2016/2017
STUDENT LEARNING TIME (SLT) Teaching and Learning Activities
Student Learning Time (hours)
1. Face-to-Face Learning a. Lecturer-Centred Learning i. Lecture
36
b. Student-Centred Learning (SCL) i. Laboratory/Tutorial ii. Student-centred learning activities – Active Learning, Project Based Learning
6
2. Self-Directed Learning a. Non-face-to-face learning or student-centred learning (SCL) such as manual, assignment, module, e-Learning, etc.
24
b. Revision
24
c.
24
Assessment Preparations
3. Formal Assessment a. Continuous Assessment (inclusive of presentation)
3.5
b. Final Exam
2.5
Total (SLT)
TEACHING METHODOLOGY
-
Lecture, tutorial and class discussion. Group Assignments, Written Quizzes and Final Examination. Active learning approach – Group hardware assignment and presentation
120
COURSE OUTLINE Department & Faculty: Electrical Engineering Faculty Course Code: SKEE 2263 Digital Systems Total Contact Hours: 42 hours
Page : 3 of 4
Semester: 1 Academic Session: 2016/2017
WEEKLY SCHEDULE Week
Test
Topic
Week 1 Sep. 4
Introduction Overview of digital system design, electronic design automation
Week 2 Sep. 11
Programmable Logic RAM, ROM, CPLD, FPGA
Week 3 Sep. 18
Number Systems Signed numbers, Fixed-point, Q number format, Intro floating point
Week 4 Sep. 25
Arithmetic Circuits I Adders: half-adder, full-adder, ripple carry adder, carry lookahead adder, carry select adder, carry save adder
Week 5 Oct. 2
Arithmetic Circuits II Subtractor, condition codes, combinational multiplier
Week 6 Oct. 9
Combinational Logic Design Case Studies Design of BCD adder, incrementer and comparator (or equivalent)
Week 7 Oct. 16
Synchronous Sequential Logic Concept of sequential logic, states, flip-flop operation and timing.
Week 8 Oct. 23
Registers
Assignment
M1 adder
M2 lpm_rom (7seg)
Test 1
M3 combinational
Design of data register, shift register, accumulator
Week 9 Oct. 30
Semester Break
Week 10 Nov. 6
FSM Modelling FSM concepts, Moore and Mealy models
Week 11 Nov. 13
FSM Analysis Analysis procedure, case studies
Week 12 Nov. 20
FSM Design FSM design procedure, design of counters, design of sequence detector
Week 13 Nov. 27
FSM Controllers Concept of datapath, controller design procedure, design of traffic light controller, design of simple vending machine controller
Week 14 Dec. 4
CU+DU Concept of Control Unit + Datapath Unit (CU+DU), Algorithmic State Machine (ASM), Design of sequential adder and bit counter
Week 15 Dec. 11
CU+DU Case Studies Design of sequential adder (or equivalent), Register Transfer Language (RTL),
M4 sequential Test 2
M5 DU
Test 3
M6 CU+DU
COURSE OUTLINE Department & Faculty: Electrical Engineering Faculty Course Code: SKEE 2263 Digital Systems Total Contact Hours: 42 hours
Page : 4 of 4
Semester: 1 Academic Session: 2016/2017
REFERENCES : 1.
Muhammad Mun’im Ahmad Zabidi, Ismahani Ismail and Izam Kamisian, Design of Digital Systems, Udan Mas, 2015.
2.
R. Katz and G. Borriello, Contemporary Logic Design. 2 ed., Prentice-Hall, 2005.
3.
F. Vahid, Digital Design with RTL Design, VHDL and Verilog. 2
4.
S. Brown and Z. Vranesic, Fundamentals of Digital Logic with Verilog Design. 3 ed., McGrawHill, 2013.
nd
nd
ed., John Wiley & Sons, 2011. rd
GRADING: Item
Marks
No. of tests/milestones
Duration
Assignments
30
6
-
Tests
20
3 (choose best 2)
2 hours
Final Exam
50
1
2.5 hours
