Design and Implementation of an Industrial Vector

Design and Implementation of an Industrial Vector Controlled Induction Motor Drive Jose Titus, Vamsikrishna M, Sekhar B, B J Rajendranath, Kamalesh Ha...

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Design and Implementation of an Industrial Vector Controlled Induction Motor Drive Jose Titus, Vamsikrishna M, Sekhar B, B J Rajendranath, Kamalesh Hatua, Krishna Vasudevan Dept. of Electrical Engineering, IIT Madras, Chennai, Tamilnadu, India. A Koteswara Rao, Shoubhik Mukherjee, S Eswara Rao, Bishnu P Muni Bharat Heavy Electricals Limited, Hyderabad, Andhra Pradesh, India. Abstract—Vector controlled induction motor drives are quite popular in the industry in applications that demand high dynamic performance. This paper describes the implementation of a complete industrial vector controlled drive for a 30 kW induction motor. The control algorithms for the drive are implemented using a TMS320F28335 Digital Signal Controller (DSC). Various monitoring and protection functions for the drive are implemented using a Cyclone IV FPGA that communicates with the DSC, and acts as the master controller for the drive. The FPGA also communicates with a Human Machine Interface (HMI) to provide a simple graphical control interface to the operator. Index Terms—Digital Signal Controller (DSC), Field Oriented Control, Human Machine Interface (HMI), Industrial Drive, Induction motor and Vector Control

I. I NTRODUCTION AC induction motor drives using vector control technique are widely employed in industrial applications requiring high dynamic performance. A typical example of such an application is the drive used in a steel rolling mill. The drives are used in power levels varying from a few kW up to the MW ranges. Modern day drives also include various built-in facilities for monitoring, protection and fault diagnosis, in addition to the basic functionality. IEEE Std 1566[1] specifies the standards and some of the desired features for an industrial drive of large rating. Also, these additional facilities should not interfere with the accuracy and speed of execution of the main control algorithms. Therefore, typical control hardware for industrial drives generally employ two separate processing units, one of which acts as a master controller and the other as a slave. The slave unit is dedicated for executing the main drive control algorithms, while the master controls

the slave and also takes care of the monitoring, protection and diagnosis functions. The master unit also has additional non-volatile memory interfaced with it for data logging of critical drive parameters. Additionally, industrial drives also have a user interface, that allows the operator to control the drive and also remotely monitor various drive parameters[2]. An overall block diagram of such an industrial drive is shown in Fig.1. Human Machine Interface (HMI)

Master Controller (FPGA)

Non−Volatile Memory

Slave Controller (DSC)

Feedback signals

Power Converter

Induction Motor

Fig. 1. Block diagram of an industrial drive

This paper describes the implementation of a complete standalone industrial drive for an induction motor, as described above. The drive is designed to operate with or without a speed sensor. The implemented drive is provided with additional special functions like self-commisioning capability, power loss ride-through and on-the-fly starting capability. The control algorithms for the drive are implemented using a TMS320F28335, which is a 32-bit floating point Digital Signal Controller (DSC). The various monitoring, protection and diagnostic facilities are implemented using a Cyclone IV FPGA device, that also acts as the master controller. The user interface for the drive is designed around a G306A modular process controller from Red Lion Controls Inc. The paper explains the manner in

which the communication between the master and slave controller is implemented, and also the sequence of processes that happen during the starting, running and stopping or tripping of the drive. The implementation of the protection and fault diagnosis facilities in the drive are also explained in detail. Section II describes the organisation of the drive in detail. The DSP-FPGA communication and the overall communication between various units of the drive are explained. The sequence of actions during various phases of drive operation are also described. Section III describes the additional functionalities of the drive like self-commissioning and ride-through capability. The implementation of various monitoring and diagnosis functions are also explained. Section IV presents and discusses some of the results obtained from the implementation of the drive. Section V discusses the conclusions from the present work. II. D RIVE O RGANISATION A. Power Structure of the drive The power structure of the drive is as shown in Fig.2. The power converter is a 35 kVA, two-level, IGBT based Voltage Source Inverter (VSI) operated at a switching frequency of 2 kHz. The rated DC bus voltage of 600 V is obtained from a front end three phase diode bridge rectifier. The firing pulses to the drive are generated from the DSC running a sensorless vector control algorithms with a loop sampling time of 100 µs. Hall effect sensors are used to sense the line currents of the machine and the DC bus voltage of the inverter, for feedback. An improved flux estimation algorithm, as reported in [3] is used for control, to obtain an excellent field orientation. With this control scheme, low-speed,

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0 1 0 1 0 1 0 1 1 0 0 1 0 1 0 00 11 1 0 1 0 1 1 0 00 11 1 0 1 0 1 0 0 1 0 1 0 1 0 1 00 11 00 11 01 1 0 11 00 0 1 0 1 0 1 0 1 0 1 0 1 00 11 0 1 0 1 0 1 M

1 00 11 0 00 11 0 1 00 11 0 1 00 11 0 1 00 11 0 1 00 11 0 1 00 11 0 1 00 11 0 00 11 0 00 11 11 00 11 00 1 1 0 00 11 11 00 10 0 11 00 11 1 0 1 0 1 0 0 1 0 1 0 1 00 11 00 11 00 11 00 11 00 11 00 11 0 1 0 1 0 1 0 1 0 1 0 1 000 11 000 11 000 11 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1

Fig. 2. Power structure of the drive

sensor-less operation upto 2.5 Hz stator frequency is achieved. B. Control platform A powerful control board is designed to take care of the sophisticated needs of the drive. The board houses the DSC and FPGA devices. Additional external Analog-Digital Converters (ADC) are also interfaced with the FPGA device. The board includes circuitry for signal conditioning of the sensed analog signals from the drive, so as to make it suitable to be fed to the ADC channels of the controllers. Additionally, level shifting and differential transmission circuitry are provided to condition the PWM signals generated from the controllers. The board also includes transcievers for several communication protocols and Digital to Analog Converter (DAC) circuits connected to both the DSC and the FPGA. It also includes additional memory chips, both volatile and non-volatile, interfaced with the controllers. All the ICs used in the board are chosen to be of industrial grade. C. Communication flow A block diagram showing the vaious communications in the drive is shown in Fig.3. The FPGA device is the master controller which communicates with both the HMI and the DSC. The FPGA processes the commands input to the HMI from the user, and controls the DSC accordingly. The communication between the HMI and FPGA is implemented via a serial link using a RS-485 transceiver IC ADM2587. A provision for RS-232 link is also provided for the HMI-FPGA communication. Further, provisions for CAN communications is provided for both the DSP and FPGA by interfacing a CAN transceiver IC with the controllers. These, along with the serial communication links may be used for future expansion by interfacing to SCADA or EMS systems. The communication between the DSP and the FPGA is based on the External Interface (XINTF) peripheral of the TMS320F28335. This peripheral allows external devices to be connected to the DSC as memory mapped peripherals. The DSC has three different XINTF zones (0, 6 and 7) each having its own chip-select, read-enable and write-enable signals. In the present drive, the XINTF zone-0 is

Master Controller (FPGA)

RS−232

RS−485

CAN

SCADA Interface for future expansion

CAN

RS−485

RS−232

Red Lion User Interface (HMI)

Slave Controller (DSC)

SPI RAM−1

by an analog protection card, based on fast opamp comparators, whose output is given to the set input of an RS latch, through a wired AND logic. The comparators compare the actual signals from the drive with a reference voltage. The output of the RS latch is used to generate an ENABLE signal that will block the PWMs on detection of any fault. Fault diagnosis is provided by additional latches wired to individual comparator outputs, whose outputs are used to drive LEDs to indicate the type of fault.

EEPROM

RAM−2

Control Board

Fig. 3. Various communications in the drive

used for implementing the DSC-FPGA interface. The XINTF is configured in the 16 bit mode with a 150 MHz clock signal. Eight GPIO lines of the DSC are configured as the address lines and connected to the FPGA, so as to address a total of 256 memory locations. Also, another 16 GPIOs are configured as the data bus and connected to the FPGA. Bidirectional communication is established between the master and slave device using two SARAM blocks configured within the FPGA. These are connected to the DSC via the XINTF. This communication is also shown in Fig.3. RAM-1 is an array of 128 memory locations of 16 bit width. The DSP is only allowed to write to these locations, while the FPGA can only read from these locations. RAM2 is similar to RAM-1, except that only the FPGA can write to it while the DSP can only read from it. Thus the communication from FPGA to DSP is established by writing into pre-determined locations of RAM-2. Similarly, communication from DSP to FPGA is achieved by writing into the locations of RAM-1.

Fig. 4. Fault Annunciation in the HMI

Secondary backup protection is provided from the FPGA side where the FPGA compares the digital signal from the ADCs with set reference values. The tripping is done by pulling the trip zone pin of the DSC low. This blocks the PWM generation from the DSP in a fast manner independent of the processor. Appropriate fault message is also sent to the HMI for display. Tertiary backup protection is provided from the DSC side using the sensed signals from the ADC. Whenever the sensed signal exceeds the reference limits, a software trip event is initiated, and the appropriate fault message information is transmitted to the FPGA for display on the HMI. However, this is a slower protection due to the execution loop time of the DSC. Fig.4 shows the D. Protection and Fault Diagnosis display on the user interface for an over-current trip Protection and Fault Diagnosis are a vital compo- from the analog protection card. nent of any drive system. It prevents operation of the drive under abnormal conditions like over-currents, E. Drive operating sequences over-voltages, over-speed etc. In the present system, The operation of the drive is divided into spethe protection is provided at three different levels cific sequences namely START, RUN and STOP in the system. The primary protection is provided sequences. These sequences describe the state of

Power Supply to all Control Cards

(FPGA) Receives the modified values

(FPGA) Sends the modified values to the DSC

HMI boots up with option to start the drive

(HMI) User modifies the default values

(FPGA) Charging contactor close command

FPGA resets DSC

START

(FPGA) Retrieve default parameters from DSC

DC volt > 80 % in 2 seconds?

YES

YES

NO

(FPGA) Drive Healthy?

(FPGA) Drive faulty on HMI

(FPGA) Close Main Contactor and Open Charging Contactor

NO

(FPGA) Drive faulty on HMI

(DSC) Release PWM signals

(FPGA) RUN command to DSC

Fig. 5. Start sequence for the drive

the drive and the response of the drive to external The DSP upon receiving the run command executes user actions or faults. The logics and program flow the control algorithms and releases the PWM pulses during each of these sequences, are described below: to the power converter. The complete flow diagram a) START sequence: The START sequence for the START sequence is shown in Fig.5. b) RUN sequence: In the RUN sequence, the describes the course of events that happen when the user issues a START command to the drive from the DSP keeps on executing the control algorithms, HMI. Initially, when the control supply is extended while the FPGA continuously communicates with to the drive, the HMI will boot up and present the the HMI to display the drive status and parameters. user with an option to START the drive. At this Fig.6 shows a display page on the HMI during the stage, the DSC is held in a reset condition by the run sequence showing the various parameters of FPGA, by pulling its RSTn pin low. When the user the drive. The RUN mode continues until a stop gives a start command, the DSC is brought out of RESET by the FPGA. The FPGA then retrieves the default values of the reference quantities and the various parameters and displays it to the user on the HMI. The user can modify these parameters on the HMI. The FPGA then receives the modified parameters and sends it to the DSP via the FPGA. The FPGA then checks for drive healthiness by monitoring a signal from the analog protection card of the drive. If the drive is healthy, the FPGA issues commands to close the charging contactor. Then, the FPGA waits for 2 seconds and checks to see if the DC bus voltage has risen to at least 80 % of its rated value. If the DC voltage has been built up, the FPGA now issues commands to open the charging contactor and close the main contactor. Fig. 6. Parameter monitoring during RUN sequence FPGA then issues the RUN command to the DSP.

command is received or the drive is tripped on a protection. c) STOP sequence: Whenever the drive receives a stop command from the operator via the HMI, the FPGA withdraws the RUN command by clearing the appropriate location in RAM-2. This blocks all PWM pulses to the drive. The FPGA then pulls the reset pin of the DSP low and issues a command to open the main contactor. III. A DDITIONAL F EATURES A. Self Commissioning scheme A self commissioning scheme as reported in [3], has been implemented in the drive. The user has to enter the nameplate details of the drive at the beginning. With this scheme, the parameters of the machine like stator resistance, stator and rotor leakage inductance, magnetising inductance and the rotor time-constant are determined automatically by the drive before starting. These are then used to tune the control loops for vector control. The leakage inductance is determined by applying a short pulse of 80 µs duration to one of the phases with the machine at standstill. Under these conditions, the machine presents only the stator resistance and leakage inductance impedance to the applied voltage. The voltage equation can be written as dis (1) Vs = Rs is + σLs dt where σLs , which denotes the stator transient inductance, can be shown to be approximately twice the stator leakage inductance. Thus with the applied step voltage pulse, the current rises linearly. The leakage inductance can be calculated directly from the slope of the current trace. Stator resistance is obtained by injecting a dc current into one phase using the inverter, while the machine is at standstill. The voltage applied to the machine is calculated from the PWM duty ratio, which is then used to calculate the stator resistance. The rotor resistance and leakage inductance are assumed to be equal to that of the stator. The rotor time constant is estimated by applying a step dc current into one of the phases and measuring the induced stator voltage. It can be shown that this voltage falls exponentially with a time constant equal to the rotor time constant. The initial slope of this falling

TABLE I E STIMATED PARAMETERS Parameter

Self Commissioning

No-load and

Scheme

Blocked Rotor test

Rs = Rr

0.1255 Ω

0.1273 Ω

Lls = Llr

1.15 mH

1.34 mH

τr

0.3587 sec

0.366 sec

voltage gives the rotor time constant. The entire estimation process is completed in less than one minute time, before the machine is started. The self-commissioning scheme is not required to be run each time before starting the machine. It is a special function which the user can invoke if so required. Table I compares the parameters obtained from the self commissioning scheme with those obtained from no-load and blocked rotor tests on the machine. B. Power Loss Ride-through Power Loss Ride-through refers to the ability of the drive to withstand a momentary power supply interruption at the grid side, without tripping. The drive should also be able to smoothly continue operation when the supply is restored. In the present drive, a regenerative scheme of ride-through as reported in [4] is implemented. In this method, the machine is made to regenerate whenever a power supply interruption is sensed. The developed torque

Fig. 7. Waveforms during regenerative ride-through Ch1- DC Bus voltage, Ch2- Angular speed, Ch3-isq , Ch4- R-phase current (Scale: X-axis: 1.0 s/div, Ch1- Y-axis: 200 V/div, Ch2- Y-axis: 455 rpm/div, Ch3- Y-axis: 15.15 A/div, Ch4- 20 A/div).

Fig. 8. Starting and a step change in speed reference. (Ch1- q-axis current, Ch2- R-phase current,Ch3- Mechanical speed in pu Scale: X-axis: 1.52 s/div, 2379 Y-axis: Ch1,Ch3- 0.225 pu/div Ch2-10 A/div)

in an induction machine can be written as Fig. 9. Developed Control Platform

Md = Kt imr isq

(2)

where imr denotes the rotor magnetising current, isq denotes the stator q-axis current and Kt is a machine parameter. Thus, by making isq negative during a supply interruption, the machine can be made to regenerate. The regenerated power is used to maintain the DC bus voltage during ride-through. With this scheme, the drive is able to withstand supply interruptions of duration up to 2 second without tripping. However, the drop in speed is dependent on the mechanical load on the machine. Fig.7 shows the waveforms in the drive for a ridethrough condition at no-load. The drop in speed and the smooth restart after supply is restored is clearly visible. IV. R ESULTS The designed drive is tested under various operating conditions. Some of the results obtained are presented below. Fig.8 shows the response of the R-phase current in the machine during starting with no-load and a step change in speed reference. The variation in speed and the q-axis current of the machine is also shown. Fig.9 shows a photograph of the developed control platform that houses the DSC and the FPGA, along with all the necessary communication transceivers, signal conditioning circuits and other peripherals.

V. C ONCLUSION This paper described an overview of the implementation of a complete industrial drive using sensorless vector control for an induction motor. The control organisation and the sequence of activities involved in starting, running and stopping of the drive are explained in detail. The communication and co-ordination between various units of the drive, and the implementation of the DSC-FPGA communication using the external interface peripheral of the DSC, are also described. The additional features of the drive like self-commissioning, ride-through and remote status monitoring are also explained. Finally, some of the results from the hardware implementation are also presented. R EFERENCES [1] “IEEE standard for performance of adjustable-speed ac drives rated 375 kw and larger,” IEEE Std 1566-2015 (Revision of IEEE Std 1566-2005), pp. 1–74, Feb 2015. [2] D. Zimmer and D. Rhodes. Human-machine interfaces. Industry Applications Magazine, IEEE, 12(2):29–35, March 2006. [3] T. Bhattacharya and L. Umanand. Improved flux estimation and stator-resistance adaptation scheme for sensorless control of induction motor. Electric Power Applications, IEE Proceedings, 153(6):911–920, November 2006. [4] J. Holtz, W. Lotzkat, and S. Stadtfeld, “Controlled ac drives with ride-through capability at power interruption,” Industry Applications, IEEE Transactions on, vol. 30, no. 5, pp. 1275– 1283, Sep 1994. [5] W. Leonhard. Control of Electrical Drives. Engineering online library. Springer Berlin Heidelberg, 2001.