Introduction to HDL Based System Design

Introduction to HDL Based System Design Presenter : Alpana Agarwal [email protected] , [email protected] Electronics & Communication Engineering D...

0 downloads 51 Views 2MB Size
Introduction to HDL Based System Design Presenter : Alpana Agarwal [email protected], [email protected]

Electronics & Communication Engineering Department

Thapar University, Patiala

Why do we Describe Systems? • Design Specification – unambiguous definition of components and interfaces in a large design

• Design Simulation – verify system/subsystem/chip performance prior to design implementation

• Design Synthesis – automated generation of a hardware design 14/12/2009

IEP on System Modeling at TU Patiala

2

1

Digital System Design Flow Requirements

• Behavioral Simulation



Register Transfer Level Design

RTL Simulation Validation



Logic Design

Logic Simulation Verification Fault Simulation

Circuit Design

Timing Simulation Circuit Analysis

Functional Design

Design flows operate at multiple levels of abstraction Need a uniform description to translate between levels Increasing costs of design and fabrication necessitate greater reliance on automation via CAD tools – $5M - $100M to design new chips – Increasing time to market pressures

Design Rule Checking

Physical Design

Description for Manufacture 14/12/2009

IEP on System Modeling at TU Patiala

3

A Synthesis Design Flow Requirements

VHDL Model

Functional Design

VHDL Model

Register Transfer Level Design

Logic Simulation

Synthesis

Behavioral Simulation (VHDL )

Place and Route

Timing Extraction

• Automation of design refinement steps • Feedback for accurate simulation • Example targets: ASICs, FPGAs 14/12/2009

IEP on System Modeling at TU Patiala

4

2

The Role of Hardware Description Languages STRUCTURAL

BEHAVIORAL algorithms register transfers Boolean expressions transfer functions

processors registers gates transistors cells modules chips boards

PHYSICAL

[Gajski and Kuhn]

• Design is structured around a hierarchy of representations • HDLs can describe distinct aspects of a design at multiple levels of abstraction 14/12/2009

IEP on System Modeling at TU Patiala

5

The Role of Hardware Description Languages STRUCTURAL

BEHAVIORAL algorithms register transfers Boolean expressions transfer functions

processors registers gates transistors cells modules chips boards

PHYSICAL

[Gajski and Kuhn]

• Interoperability: models at multiple levels of abstraction • Technology independence: portable model • Design re-use and rapid prototyping 14/12/2009

IEP on System Modeling at TU Patiala

6

3

Traditional vs. Hardware Description Languages • Procedural programming languages provide the how or recipes – for computation – for data manipulation – for execution on a specific hardware model

• Hardware description languages describe a system – Systems can be described from many different points of view • • • •

Behavior: what does it do? Structure: what is it composed of? Functional properties: how do I interface to it? Physical properties: how fast is it?

14/12/2009

IEP on System Modeling at TU Patiala

7

VHDL • What is VHDL? V H I S C  Very High Speed Integrated Circuit Hardware Description IEEE Standard 1076-1993

Language 14/12/2009

IEP on System Modeling at TU Patiala

8

4

History of VHDL • Designed by IBM, Texas Instruments, and Intermetrics as part of the DoD funded VHSIC program • Standardized by the IEEE in 1987: IEEE 1076-1987 • Enhanced version of the language defined in 1993: IEEE 1076-1993 • Additional standardized packages provide definitions of data types and expressions of timing data – IEEE 1164 (data types) – IEEE 1076.3 (numeric) – IEEE 1076.4 (timing)

14/12/2009

IEP on System Modeling at TU Patiala

9

Usage • Descriptions can be at different levels of abstraction – Switch level: model switching behavior of transistors – Register transfer level: model combinational and sequential logic components – Instruction set architecture level: functional behavior of a microprocessor

• Descriptions can used for – Simulation • Verification, performance evaluation

– Synthesis • First step in hardware design

14/12/2009

IEP on System Modeling at TU Patiala

10

5

The Marketplace Maximum revenue

r is e ke t

fa

M ar

t ke ar M ll

Revenue

Revenue loss

From V. K. Madisetti and T. W. Egolf, “Virtual Prototyping of Embedded Microcontroller Based DSP Systems,” IEEE Micro, pp. 9–21, 1995.

Delay Time



Time to market delays have a substantial impact on product revenue • First 10%-20% of design cycle can determine 70%-80% of the cost • Costs are rising rapidly with each new generation of technology • Need standards and re-use  automation centered around HDL based tools such IEP as VHDL 14/12/2009 on System Modeling at TU Patiala

11

Alternatives • The Verilog hardware description language – Finding increasing use in the commercial world • SystemVerilog gaining prominence

– VHDL dominates the aerospace and defense worlds

• Programming language based design flows – SystemC • C++ with additional hardware-based language elements

– C-based design flows • C + extensions as well as ANSI C based

– Other • Java, MATLAB, and specialized languages 14/12/2009

IEP on System Modeling at TU Patiala

12

6

Systems Hierarchy

Level of Abstraction Functions

CPUs, memories

Increasing •Fidelity •#of events

The link ed image cannot be display ed. The file may hav e been mov ed, renamed, or deleted. Verify that the link points to the correct file and location.

ALUs, registers

Switches

14/12/2009

IEP on System Modeling at TU Patiala

13

Describing Systems microphone To the Processor

headphones ZPS 61899 speakers amplifier



From Webster’s Dictionary: – System: “An assemblage of objects united by some form of regular interaction or dependence”



What aspects of a digital system do we want to describe?

– Interface – Function: behavioral and structural 14/12/2009

IEP on System Modeling at TU Patiala

14

7

What Elements Should be in a Description? • Descriptions should be at multiple levels of abstraction – The descriptive elements must be common to multiple levels of hierarchy

• The elements should enable meaningful and accurate simulation of hardware described using the elements – Elements should have attributes of time as well as function

• The elements should enable the generation of hardware elements that realize a correct physical implementation – Existence of a mapping from elements to VLSI devices

14/12/2009

IEP on System Modeling at TU Patiala

15

What Elements Should be in a Description? • VHDL was conceived for the description of digital systems – From switches to networked systems

• Keep in mind the pragmatic issues of design re-use and portability of descriptions – Portability across technology generations – Portability across a range of cost/performance points

• Attributes of digital systems serve as the starting point – Language features designed to capture the key attributes 14/12/2009

IEP on System Modeling at TU Patiala

16

8

Attributes of Digital Systems Event a

a b

b

sum carry

sum carry 5

10

15

20 25 Time (ns)

30

35

40

• •

Digital systems are about signals and their values Events, propagation delays, concurrency



Time ordered sequence of events produces a waveform

– Signal value changes at specific points in time

14/12/2009

IEP on System Modeling at TU Patiala

17

Attributes of Digital Systems: Timing R

Clk Triggering edge

Q

D

D

Q Clk

Q 10

• • •

15

20 25 30 Time (ns)

35

40

S

Timing: computation of events takes place at specific points in time Need to “wait for” an event: in this case the clock Timing is an attribute of both synchronous and asynchronous systems

14/12/2009

IEP on System Modeling at TU Patiala

18

9

Attributes of Digital Systems: Timing TRANSMIT

ACK

• • •

Example: Asynchronous communication No global clock Still need to wait for events on specific signals

14/12/2009

IEP on System Modeling at TU Patiala

19

Attributes of Digital Systems: Signal Values • We associate logical values with the state of a signal possible signal values?

• Signal Values: IEEE 1164 Value System Value

14/12/2009

Interpretation

U

Uninitialized

X

Forcing Unknown

0

Forcing 0

1

Forcing 1

Z

High Impedance

W

Weak Unknown

L

Weak 0

H

Weak 1

-

Don’t Care

IEP on System Modeling at TU Patiala

20

10

Attributes of Digital Systems: Multiple Drivers



Shared Signals

– multiple drivers •

How is the value of the signal determined?

– arbitration protocols – wired logic 14/12/2009

IEP on System Modeling at TU Patiala

21

Modeling Digital Systems •

We seek to describe attributes of digital systems common to multiple levels of abstraction – events, propagation delays, concurrency – waveforms and timing – signal values – shared signals



Hardware description languages must provide constructs for naturally describing these attributes of a specific design – simulators use such descriptions for “mimicing” the physical system – synthesis compilers use such descriptions for synthesizing manufacturable hardware specifications that conform to this description

14/12/2009

IEP on System Modeling at TU Patiala

22

11

Execution Models for VHDL Programs • Two classes of execution models govern the application of VHDL programs • For Simulation – Discrete event simulation – Understanding is invaluable in debugging programs

• For Synthesis – Hardware inference – The resulting circuit is a function of the building blocks used for implementation • Primitives: NAND vs. NOR • Cost/performance 14/12/2009

IEP on System Modeling at TU Patiala

23

Simulation vs. Synthesis entity my_ckt is port (x, y : in bit ; z : out bit ) end entity my_ckt; behavioral architecture my_ckt is begin

of

synthesis

-- some code here -end architecture behavioral; entity my_ckt is port (x, y :in bit ; z : out bit ) end entity my_ckt; architecture behavioral my_ckt is begin

simulation of

-- some code here -end architecture behavioral;



Simulation and synthesis are complementary processes

14/12/2009

IEP on System Modeling at TU Patiala

24

12

Simulation of Digital Systems @5 ns @5 ns

@15 ns

0 @10 ns

Head

v1v2 @5ns

• •

v3v4 @10ns

v5v6 @15ns

Digital systems are modeled as the generation of events – value transitions – on signals Discrete event simulations manage the generation and ordering of events – Correct sequencing of event processing – Correct sequencing of computations caused by events

14/12/2009

IEP on System Modeling at TU Patiala

25

Discrete Event Simulation: Example Simulation Time

Event List Head Initial state: a = b = 1, sum = carry = U

0ns

U1 [email protected]

U0 [email protected]

U1 [email protected]

U0 [email protected]

10 [email protected]

10 [email protected]

01 [email protected]

01 [email protected]

New event generated from input

Update time

5ns Update signal values, execute, generate new events, update time

10ns Update signal values, execute, generate new events

10 [email protected]

Event a

10ns

10 [email protected]

b

sum

a b

sum carry 5

10

15

20

25

30

35

40

carry

14/12/2009

IEP on System Modeling at TU Patiala

26

13

Discrete Event Simulation •

Management of simulation time: ordering of events



Two step model of the progression of time – Evaluate all affected components at the current time: events on input signals – Schedule future events and move to the next time step: the next time at which events take place

14/12/2009

IEP on System Modeling at TU Patiala

27

Simulation Modeling a b

sum VHDL Model carry

compiler

Discrete Event Simulator from Vendor

• • •

VHDL programs describe the generation of events in digital systems Discrete event simulator manages event ordering and progression of time Now we can quantitatively understand accuracy vs. time trade-offs – Greater detail  more events  greater accuracy – Less detail  smaller number of events  faster simulation speed

14/12/2009

IEP on System Modeling at TU Patiala

28

14

Synthesis and Hardware Inference Design Specification

HDL

Author HDL Author Hardware Design

Synthesi s engine

• Both processes can produce very 14/12/2009 IEP on System Modeling at TU Patiala different results!

29

Summary • VHDL is used to describe digital systems and hence has language constructs for key attributes – Events, propagation delays, and concurrency – Timing, and waveforms – Signal values and use of multiple drivers for a signal

• VHDL has an underlying discrete event simulation model – Model the generation of events on signals – Built in mechanisms for managing events and the progression of time – Designer simply focuses on writing accurate descriptions 14/12/2009

IEP on System Modeling at TU Patiala

30

15

References • • • • • • •

S. Yalamanchili, Introductory VHDL : From Simulation to Synthesis, Prentice-Hall, 2000. (Cheap Edition) P. J. Ashenden, The Designer's Guide to VHDL, Second Edition, Elsevier/MK, 2001. (Cheap Edition) J. Armstrong and F. G. Gray, VHDL Design Represent-ation and Synthesis, Second Edition, Prentice-Hall, 2000. J. Bhasker, A VHDL Primer, Third Edition, Prentice-Hall, 1999. (Cheap Edition) J. Bhasker, A VHDL Synthesis Primer, Second Edition, Star Galaxy, 1998. (Cheap Edition) IEEE Standard 1076-1993, VHDL Langauge Reference Manual, IEEE Press, 1993. Z. Navabi, VHDL : Analysis and Modeling of Digital Systems, Second Edition, McGraw-Hill, 1998. (Cheap Edition)

14/12/2009

IEP on System Modeling at TU Patiala

31

Thank You

16