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Journal of Engineering Science and Technology Vol. 14, No. 2 (2019) 629 - 628 © School of Engineering, Taylor’s University

LEAKAGE IMMUNE SINGLE ENDED 8T SRAM CELL FOR ULTRA-LOW POWER MEMORY DESIGN HITESH PAHUJA1, MINTU TYAGI2, BALWINDER SINGH1,*, SUDHAKAR PANDAY3 1Centre

for Development of Advanced Computing, Ministry of Electronics and Information Technology, Mohali, Punjab, 160071, India 2Department of Electronics and communication, Desh Bhagat University, 3Department of Electronics and Communication, Eternal University, Baru Sahib, HP, India *Corresponding Author: [email protected]

Abstract As the technology is advancing into deep submicron and as the size of the devices is scaled down, a number of issues are faced during the manufacturing of these computing devices. These critical issues include power consumption, size, and speed of electronic devices. Generally, the chip contains millions of transistors. Therefore, a lot of issues are associated with the working of these transistors among which, power dissipation is one of the important design concerns. In this paper, new low power 8T SRAM cell is proposed, which improves the leakage power, access time compared to 6T SRAM, 5T SRAM, and conventional 8T SRAM cell. Simulation and analytical results show that proposed 8T SRAM cell reduces leakage power by 83.54% compared to the conventional 8T cell, 73.27% compared to 6T SRAM cell and 86.1% compared to 5T SRAM cell. The access time of a new 8T cell is improved by 13.75% compared to 6T SRAM cell, 45.2% compared to conventional 8T SRAM cell and 49.20% compared to 5T SRAM cell. The proposed SRAM cell also reduces leakage current dramatically as compared to 6T SRAM cell, conventional 8T SRAM, and 5T SRAM cell Keywords: Leakage current, Power, Delay, SRAM, Stability, System on chip.

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1. Introduction Semiconductor memories have the most important part of modern VLSI systems. It is the most important component in a System on Chip (SOC) nowadays. Roy and Prasad [1] reported that almost all system on a chip contains memories like flash memory, Read Only Memory (ROM), Static Random-Access Memory (SRAM) and Dynamic Random-Access Memory (DRAM). The memory stores data as well as instructions used in modern technology such as portable devices, computer and electronic gadgets. Memory is either volatile or non-volatile. Volatile memory loses data when power is switched off whereas non-volatile memory stores data indefinitely. SRAM and DRAM are the volatile memory, which saves data by using transistors and capacitors respectively. Non-volatile memories like ROM, Erasable Programmable Read Only Memory (EPROM) and flash memory stores data permanently. It can be reprogrammable according to user need [1]. According to the International Technology Roadmap for Semiconductor (ITRS), more than 90% of the integrated chip area will be covered by memory in the coming years. As reported in the ITRS road map, transistor devoted to memory structure in a typical embedded system is around 70% presently and expected to increase to 80% in future [2-4]. Power is one of the vital resources hence, the designers are trying to reduce it while designing a system [5]. The major challenge in portable electronics devices is to reduce their power dissipation. In deep submicron technology, the leakage power component becomes a significant percentage of the total power and the leakage current increases at a faster rate than dynamic power for below 100 nm technology generations. That is why the leakage power has become an important issue [1, 6, 7]. Memory, especially cache is considered to be the major part of any computing devices, therefore, the power dissipation of memory is of major concern for any design [3-8]. Praveen and Shivaleelavathi [9] explained that the variation in the process parameter is because of aggressive scaling of technology creates a lot of issues in yield, reliability and testing. Moghaddam et al. [10] stated that generally, it is said that for every 10-degree rise in temperature the failure rate of a VLSI chip become doubles.

2. Related Research The conventional 6T SRAM cell is as shown in the following Fig. 1(a). It is the most common industry standard used for the organization of the SRAM [10]. It is having two PMOS, i.e., M3 and M4 shown in blue colour and four NMOS transistors, i.e., M1, M2, M5, M6 highlighted in red colour. In this structure, the two inverters are used in the cross-coupled configuration. During the write operation, the logic ‘1’ is provided to Word Line (WL) and required data can be written on the bit lines. Whereas, during the read operation, the bit lines are pre charged to half of Vdd with WL is kept at a high value. Therefore, one sourcing and one sinking current will flow through the bit lines, which is sensed by the sense amplifier [11]. Hence, the corresponding output is produced at the output of the sense amplifier. When the WL is not activated, the pass transistors access left and access right detaches the bit cell from the bit lines. Prasad and Anand [12] explained that the cross-connected inverter pair formed by p-left, p-right, n-

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left and n-right will continue to reinforce each other as long as they are connected to the supply and the small amount of leakage power will occur in the cell due to leakage currents in the MOS devices, which is known as the static or standby power dissipation in the memory cell. As illustrated in Fig. 1(a) that read problem in the conventional 6T SRAM cell during a stored data access, the increased voltage of QB node from nil to VL value, which further drives the inverter (M4-M2) by activating gate voltage and might destruct the stored value, especially in the sub-threshold regime [4, 11]. The conventional 8T SRAM cell is based on splitting the trade-off among the write and read operations by employing a buffer that separates from the internal nodes Q and QB. However, it requires a larger area or using a single-ended read port, which results in a slightly reduced read sensitivity. As shown in Fig. 1(b), the 8T SRAM cell has used two transistors called M8 and M7 connected in series for only read access to eliminate the read operation problem like power dissipation and stability [4, 13]. According to Akashe and Sharma [8], 5T SRAM cell comprises of five transistors. NMOS transistors (NM1 and NM0) shown in red colour. Whereas, PMOS transistors (PMO, PM1 and PM2) represented with blue notation. It comprises a one-bit line, a one-word line along with extra read-line control. The designed cell has taken 21.66% less area as compared to the conventional 6T SRAM cell. The 5T SRAM cell is designed based on feedback cutting transistors during idle mode to reduce leakage current and improved power, which has been reported as shown in Fig. 2. The 5T cell reported 72.10% less leakage current as compared to 6T SRAM cell at 45 nm technology. In the recent applications, area, power and performance are all very essential parameters to be monitored while designing. Previously, the power, which is dominated by dynamic power, which has been controlled by dropping the supply voltage. The supply voltage for sub-threshold static random-access memories (SRAM) has reached around 0.5 V. Supply voltage (Vdd) downscaling increases the transistor mismatch but reduces the crucial parameters.

(a)

(b) Fig. 1(a) 6T SRAM cell, (b) 8T cell.

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Fig. 2. Schematic of 5T SRAM cell.

3. Proposed Circuit Description The proposed SRAM cell consists of 8 transistors. The six NMOS transistor is represented in red colour and two PMOS transistors are represented in blue colour as shown in Fig. 3. The design is implemented using cadence virtuoso tool at 45 nm process technology. The proposed 8T SRAM cell reduces the leakage power consumption during write and standby mode compared to a conventional SRAM cell. Moreover, it improves the stability compared to the conventional cell. The presented SRAM cell consists of 8 transistors, in which, two inverters (PM0, NM0 and PM1, NM1) are associated in a cross-connected manner and NM2 is only one right pass transistor, which is on by single word line during read and write operation. NM3 and NM4 are used with reading circuitry to read out the stored data in the SRAM cell. In our presented SRAM, the read operation is performed by activating read bit line RBL. While WBL is employed for the write operation of the proposed cell. The innovative in SRAM cell is a single bit line for a write operation, which improves stability and reduces power during write and holds mode. The transistor NM5 is employed as virtual ground by applying the WL signal at the gate terminal. During operation, it forms transistor stacking [14-17], which reduces leakage current whereas, in standby mode, NM5 is disconnected as a word line is low, thus, it creates virtual ground, which saves a large amount of leakage power in a proposed circuit. Total leakage power is reduced dramatically by adding a tail transistor in the ground path, which works dual role of stack effect as well as virtual ground [1317]. Hence, large power is saved while flowing of current from source to ground.

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Fig. 3. Proposed 8T SRAM cell schematic.

3.1. Circuit operation As shown in Fig. 3 during write 1 operation, write bit-line is at an active high level to store data '1' in the SRAM cell by providing Word Line (WL) to a high value. Similarly, SRAM cell performs write '0' operation by Write Bit Line (WBL) to low value and WL to a high value to get the desired value stored in the SRAM cell. During write '1' data into SRAM cell, WBL is charged to supply voltage Vdd by activating NM2 using WL to be enabled. As the WBL is set at logic high value '1’. The ST node going to charge, which turn on NM1 and leads to flip STB node to logic low value '0’. At the same time, STB node helps PM0 to be enabled, which assist good write value logic 1 at ST node. Similarly, during write '0' operation, WBL should be at a logic low value, the access transistor is on by enabling WL signal. The ST node now discharges, which turns on the PM1, which causes flip STB node to high value '1’, on the other end STB node helps NM0 to turn on, which assist in discharging ST node accurately, thus, logic 0 is stored in our cell. The waveforms of write operation consist of bit lines, word line, Readbitline (RBL), Q and Qbar nodes has been shown in Fig. 4. To perform read operation in our cell, we have implemented a proper read circuitry to avoid read delay. The Read Bit-Line (RBL) is pre-charged to half of the voltage supply (Vdd). After applying the voltage supply at RBL the read-out signal is generated properly at the output end. If the read bit line is being discharged after pulling up read line to Vdd, it shows that logic '0' is stored in the SRAM cell. If the bit line holds the stored charge, then logic '1' is stored in proposed SRAM. In standby mode, Word Line is not asserted (WL=0), therefore, access transistor NM2, which connects proposed SRAM cell from bit line are turned off. It means that data into the bit cell unable to access. The two cross connected inverters will continue to feedback, until both are connected to the power supply. Thus, data will continue to be stored in the latch as shown in Fig. 3. During Standby mode Word Line (WL) is not enabled. The data written in the SRAM cell will be stored as long as the cell is connected to Vdd supply. The value stored in standby mode is at ST node and complement of data is stored in the STB node. The data either '0' or '1' will be retained in the SRAM cell as long as power supply is 'ON’.

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Fig. 4. Write operation of proposed SRAM cell.

3.2. Standby mode analysis In the large SRAM array, most of the bit cells are in standby state, which dominates the overall power consumption. Standby mode is also known as hold state. In this mode, no operation is performed neither read nor write. The data written in SRAM cell is stored at ST node and it is held in latch as long as the new value to be written in the cell. The standby mode further comprises of two modes, i.e., hold '1' mode and hold '0' mode. The proposed SRAM cell consists of 8 transistors. The six NMOS transistor is represented in red colour and two PMOS transistors are represented in blue colour as shown in Fig. 5. During hold '1' mode NM2, NM0 and NM5 transistors are off in series. Therefore, these transistors constitute stack effect or self-reverse bias, which reduces leakage current dramatically compared to conventional 6T SRAM, 5T SRAM and conventional 8T SRAM cell. Sub-threshold leakage current, when flowing through a series connected transistors has been reduced because of stacking effect, as more than one or two transistors in the stack are in the cut-off state [14, 17]. As NM5 transistor is connected to the word line, which is not asserted in standby mode. Thus, transistor NM5 is off and worked as a switch with increased ground voltage called virtual ground, which reduces leakage current from source to ground. The NM5 transistor works as the dual role of stack effect and virtual ground in standby mode, which reduces static power dissipation. During Hold '0' mode transistors, NM1 and NM5 are in the cut-off state. Thus, constitute stack effect of two off transistors in series, which reduces more leakage current as compared when a single transistor is off. The NM5 also act as a virtual ground in both hold '0' and '1' mode. Thus, prevents leakage current from source to ground terminal. The transistor NM5 act as virtual ground during the standby mode [12-16].

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(a)

(b)

Fig. 5. Standby mode analysis (a) Hold ‘1’, (b) Hold ‘0’.

4. Simulation Results and Discussions The results have been compared in cadence spectre simulator at 45 nm process technology at 1.1 V between 6T cell, conventional 8T SRAM [4], 5T SRAM [8] and proposed SRAM cell in terms of leakage current at ST node during write 1 and write 0, leakage current of cell during idle mode, average power dissipation, static power dissipation, cell delay, and area.

4.1. Sub-threshold leakage current Raj and Jain [17] and Kushwah and Sikarwar [18] commented that the subthreshold leakage current is basically a drain to source leakage current, which flows when a transistor is switched off. It flows between drain to source terminal during weak inversion mode, i.e., when gate-source voltage (Vgs) is less than the threshold voltage (Vth) [10]. The drain to source current (Ids) flows due to the diffusion current of minority charge carriers during weak inversion state [19]. The sub-threshold leakage current [18] is expressed mathematically as shown in Eq. (1) 𝐼𝑠𝑢𝑏 = 𝐵𝑒

𝑉𝑔𝑠−𝑉𝑡ℎ+𝜂𝑉𝑑𝑠−ϒ𝑉𝑠𝑏 𝑛𝑉𝜃

(1 − 𝑒

−𝑉𝑑𝑠 𝑉𝜃

)

(1)

where, B = µCox(W/L) Vθ e1.8, W = width, L = length, µ = carrier mobility, Vθ is thermal voltage, η is drain induced barrier lowering coefficient and n is subthreshold swing coefficient. Process of calculating leakage current Leakage current is calculated in that transistor, which is in the cut-off state through a write operation of the bit cell [8, 20]. There are two nodes, i.e., write 1 at ST node and write 0 at ST node. The amount of leakage current at the storage node represents a cell capability in writing data in the memory. The less is current at nodes defined a better write ability [20].  For write 1 in ST node Based on studies by Akashe and Sharma [8] and Akashe et al. [20], during write 1 in ST node, transistor PM1 and NM0 are in off state, therefore, we will calculate

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leakage current at nodes of cut-off transistors. The NMOS and PMOS leakage current waveform as shown in Fig. 6.  For write 0 in ST node During write 0 at ST node, transistor PM0 and NM1 are turned off, therefore, we can calculate leakage current of PMOS and NMOS (cut-off transistors) highlighted in red and green colour respectively shown in Fig. 7.  For write 1 in ST node During write 1 at ST node, transistor M2 and M3 are turned off, therefore, we can calculate leakage current at nodes of cut-off transistors [8], which is shown in Fig. 8.  For write 0 in ST node Similarly, as shown in Fig. 9, during write 0 in ST node, transistor M4 and M1 are in off state, therefore, we will calculate leakage current at nodes of cut-off transistors. Table 1 shown below that proposed 8T SRAM cell leakage current in write '0' ST node and write '1' ST node is less than conventional 8T SRAM cell [4] and conventional 6T SRAM cell. Therefore, proposed SRAM cell is better in writing data in the memory.

Fig. 6. Leakage current during write'1' at ST node of proposed SRAM cell.

Fig. 7. Leakage current during write '0' at ST node of proposed SRAM cell.

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Fig. 8. Leakage current during write '1' at ST node of conventional 8T SRAM.

Fig. 9. Leakage current during write '0' at ST node of conventional 8T SRAM. Table 1. Comparison of leakage current during write operation at storage. Leakage current Write ‘1’ Write '0’

Conventional 8T SRAM [4] NMOS 106.8 µA 3.9 pA

PMOS 58.0 µA 2.6 pA

Conventional 6T SRAM NMOS 5.7 pA 5.7 pA

PMOS 5.6 pA 5.6 pA

5T SRAM [8] NMOS 7.79 pA

PMOS 5.9 pA 10.7 pA

Proposed 8T SRAM cell NMOS 3.9 pA 5.7 pA

PMOS 2.7 pA 2.7 pA

4.2. Total leakage current (I leakage) The leakage current of the SRAM cell is calculated when a circuit is in an idle time that is no operation is performed. The current flows during an idle period from Vdd to ground when a circuit is holding stored value, small leakage current flow from drain to source in all cut-off transistors [20]. Table 2 shows the total leakage current in the proposed SRAM cell is dramatically reduced compared to conventional 8T, 5T SRAM, and conventional 6T SRAM cell. Further, we have analysed the leakage current with compared SRAM cell in Fig. 10. It has been found that the proposed SRAM has lower leakage current compared to other SRAM cells.

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Table 2. Comparison of total leakage current in idle mode. SRAM Cell I leakage

6T SRAM 24.18 pA

5T SRAM 46.5 pA

Conventional 8T 39.27 pA

Proposed 8T 6.46 pA

Fig. 10. Leakage current comparison of compared SRAM cells.

4.3. Power consumption Power consumed in SRAM cell depends on the consumption of power of all transistors used for read and write operations [17]. Power dissipation occurs during read and write operation tends to be dynamic power dissipation [21]. Dynamic power dissipation is mathematically represented by Eq. (2). 𝑃𝑎𝑣𝑔 = 𝛼. 𝐶𝑙𝑜𝑎𝑑. 𝑉𝑑𝑑 2 . 𝑓𝑐𝑙𝑘

(2)

Switching activity factor and total load capacitance of the circuit is denoted by α and Cload respectively. Vdd and fclk is the supply voltage and the operating frequency respectively. The average power is directly proportional to the α. The power dissipation can be minimized by controlling the switching activity, supply voltage and the load capacitance during operation of SRAM cell [22]. Whereas, Static power dissipation is the leakage power when a circuit is idle or circuit is not switching [23]. When the gate voltage is below the threshold voltage (Vth) then undesired leakage current flow between the source and drain in a MOS transistor [24, 25]. It plays a dominant factor as compared to dynamic power because most of the time memory circuitry remains in an idle state [26]. It is represented mathematically by Eq. (3) 𝑃𝑠𝑡𝑎𝑡𝑖𝑐 = 𝐼𝑙𝑒𝑎𝑘𝑎𝑔𝑒. 𝑉𝑑𝑑

(3)

In the proposed SRAM cell leakage power has been reduced as compared to 6T SRAM cell, conventional 8T SRAM cell and 5T SRAM cell respectively, whereas average power (dynamic and static) dissipation of new SRAM is reduced compared to conventional 8T SRAM, however, increases as compared to 6T and 5T SRAM cell, which is shown in Table 3. Furthermore, the comparison chart of static power represented with a blue colour and average power dissipation in red colour between 6T, 5T SRAM, conventional 8T and proposed 8T SRAM is analysed in Fig. 11. The average dynamic power dissipation is calculated by transient analysis at 10 ns with a pulse duration of 3 ns, which is reported to be a 10.9 μw and waveform

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of average power dissipation is shown in Fig. 12. The static power dissipation has been a critical issue in designing memories. Static power consumption is nowadays a very crucial parameter in designing of SRAM. Leakage current is responsible for static power dissipation during standby mode and it is increasing dramatically in deep submicron technology. Static power dissipation is calculated by defining a stimulus file where all inputs are DC voltage sources. This ensures that no switching activity is happening in the circuit. Since there is no switching activity in the circuit, power waveform should be a straight line in cadence virtuoso tool. Hence, power during idle mode is calculated [27]. Furthermore, static power dissipation during write 1 and write 0 is also very crucial to monitored while designing SRAM cell, the experimental results show that proposed SRAM consumes low power during write 1 and write 0 operations, which are compared in Table 4. Whereas, in Fig. 13, the results of static power dissipation during a write operation is analysed between proposed SRAM cell, convention 6T SRAM, conventional 8T SRAM cell and 5T SRAM cell [8]. Table 3. Comparison of static and average power consumption. SRAM cell Static power Average power

6T SRAM 26.6 pw 1.49 µw

5T SRAM

Conventional 8T

Proposed SRAM

Better performance

51.2 pw

43.2 pw

7.11 pw

Proposed SRAM

10.9 µW

6T SRAM

2.04 µw

16.1 µw

Table 4. Static power dissipation during write 0 and write 1. SRAM cell PSTATIC during write 1 PSTATIC during write 0

6T SRAM

5T SRAM

Conventional 8T

Proposed SRAM

Better performance

36.1 pw

48.8 pw

42.2 pw

36.16 pw

Proposed SRAM

36.3pw

34.7pw

36.14 pw

3.49 pw

Proposed SRAM

Fig. 11. Comparison chart of static and average power dissipation.

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Fig. 12. Average power dissipation of proposed 8T SRAM cell.

Fig. 13. Static power dissipation during write operation.

4.4. Delay The propagation of signal delay defines the signal timing delay from input to output during transitions of the output from a high value to low value and vice versa respectively [11]. Where TPHL is defined as the timing delay between the 50% transition of the elevating input voltage and falling output voltage respectively. Whereas, TPLH is vice-versa of TPHL [11]. Hence, to streamline the mathematical analysis of signal delay terminologies, the waveform of an input voltage is mostly supposed to be an ideal unit step pulse. Therefore, TPHL assumed to be the time needed for the Vout to fall down from VOH to the V50% level. Similarly, TPLH is the time taken for the Vout to increase from VOL to the V50% level. The voltage points V50% is mathematically expressed in Eq. (4). 1

1

2

2

𝑉50% = 𝑉𝑂𝐿 + (𝑉𝑂𝐻 -𝑉𝑂𝐿 )= (𝑉𝑂𝐻 +𝑉𝑂𝐿 )

(4)

Therefore, the propagation delay times that is TPHL and TPLH are calculated as shown in Eqs. (5) and (6) respectively. 𝑇𝑃𝐻𝐿

= 𝑡1 − 𝑡0

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𝑇𝑃𝐿𝐻

= 𝑡3 − 𝑡2

(6)

The Tavg is defined as average propagation delay and it exemplifies the average time desired for an input signal to proliferate through the CMOS inverter. It is represented as in Eq. (7).

Tavg=

TPLH+TPHL 2

(7)

SRAM cell delay is calculated directly by using the cadence virtuoso tools at 45 nm process technology. The cell delay is calculated by using a calculator in cadence spectre simulator after the simulation of three circuits. Hence, we can calculate the delay in both the condition for ST node and for STB node. The delay will be calculated by using the basic idea, which is shown in Fig. 14. The values of cell delay in time amongst conventional 6T SRAM, 5T SRAM [8], conventional 8T SRAM [4] and proposed 8T SRAM cell is given in Table 5 and comparison among different SRAM cells is shown in Fig. 15. The writing data is better in proposed SRAM cell when compared to other techniques due to employing of low Vt access transistor (NM2). Because the write delay is directly proportional to the threshold voltage of access transistor. Hence, the write delay is reduced in the proposed SRAM cell as compared to other techniques [1, 11]. Table 5. Cell delay comparison of compared SRAM cells. Parameter Delay at STB node Delay at ST node

Delay of 6T

Delay of 5T

Delay of conventional 8T cell

Delay of proposed 8T cell

Better performance

18.11 ps

51.38 ps

16.1 ps

15.62 ps

Proposed 8T

21.17 ps

40.12 ps

37.2 ps

20.38 ps

Proposed 8T

Fig. 14. Waveform of typical inverter for delay calculation.

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60 50 40 30 20

10 0 Delay at STB node

Delay at ST node

6T SRAM

Conventional 8T SRAM

5T SRAM

Proposed 8T SRAM

Fig. 15. Cell delay comparison chart of SRAM cells.

4.5. Area In Table 6 below shows that a number of transistors used and the area occupied on the chip in case of SRAM cells, i.e., proposed 8T SRAM cell, 5T SRAM cell, 6T SRAM cell and conventional 8T cell. The layout is generated in Cadence virtuoso tool [9]. Design rule check has been checked for width, spacing, enclosure and minimum area. The proposed and compared SRAM cells follows minimum spacing between two objects along with a minimum width of each and every shape in the design. Moreover, it employed a minimum area rule. The proposed SRAM cell occupies a larger area than 6T cell and 5T SRAM cell whereas the area of the proposed cell is approximately the same as a conventional 8T bit cell. The values of length, width and area are varied by varying the aspect ratio (W/L ratio) of each transistor in the proposed 8T SRAM cell, which is different as compared to conventional 8T SRAM cell to achieve minimum delay along with lesser power dissipation. The proposed cell is far better in terms of static power, leakage current and delay as compared to 6T SRAM cell, 5T SRAM cell and conventional 8T SRAM on compromising larger area as compared to 6T SRAM cell and 5T SRAM cell. In Table 6, comparison of a number of transistors, length, width and area between 6T, 8T, 5T and proposed 8T SRAM cell is given below. The layout is drawn in cadence virtuoso tool of the conventional 6T SRAM cell and proposed 8T SRAM cell has been shown in Figs. 16(a) and (b) respectively. Table 6. Area comparison of compared SRAM cells. Transistors

Length (µm)

Width (µm)

Area (µm2)

6T SRAM Cell

6

1.80

1.91

3.438

5T SRAM cell

5

1.75

1.54

2.695

Conventional 8T cell Proposed SRAM

8

2.09

2.19

4.577

8

2.01

2.26

4.560

SRAM Cell

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Fig. 16. (a) Layout of proposed 8T SRAM cell, (b) 6T SRAM cell.

5. Conclusion In the reported work, simulation has been performed using 45 nm process technology at 1.1 v. Here, we have calculated the leakage current at ST and STB nodes, Leakage power, average power dissipation, leakage current in standby mode, propagation delay, area of the proposed SRAM cell. Further, the results have been compared with conventional 6T, conventional 8T SRAM cell and 5T SRAM cell. The savings in leakage power of the proposed SRAM cell as compared to the 6T SRAM cell is 73.27% and 83.54% when compared to conventional 8T cell and 86.1% when compared to 5T SRAM cell. The average power dissipation of the proposed SRAM cell is decreased by 32.3% as compared to a conventional 8T SRAM cell. While it is increased by 86.3% as compared to the conventional 6T cell. The proposed cell has 24.6% extra area overhead as compared to the 6T SRAM cell and 40.89% from 5T SRAM cell. Whereas, it is almost approximately the same as a conventional 8T SRAM cell. Thus, our proposed cell is better in leakage current, which improves battery life of the latest gadgets like smartphones, laptops, neural signal processors and other portable applications.

Nomenclatures Tavg Isub Pavg Pstatic TPHL V50%

Average propagation delay Subthreshold leakage current Dynamic power dissipation Static power dissipation Propagation delay time Voltage point

Greek Symbols Α Switching activity factor Drain induced barrier lowering coefficient  µ Carrier mobility

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Abbreviations DRAM EPROM MOS ROM SOC SRAM VLSI

Dynamic Random-Access Memory Erasable Programmable Read Only Memory Metal Oxide Semiconductor Read Only Memory System on Chip Static Random-Access Memory Very Large-Scale Integration

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Journal of Engineering Science and Technology

April 2019, Vol. 14(2)