Microcontrollers and Interfacing

Microcontrollers and Interfacing week 7 exercises 1 Serial to parallel conversion ... program to correctly operate the 74HC595, testing it with some o...

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SERIAL TO PARALLEL CONVERSION

Microcontrollers and Interfacing week 7 exercises

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Serial to parallel conversion

Using many LEDs (e.g., several seven-segment displays or bar graphs) is difficult, because only a few digital outputs are available. If each signal (LED) has one dedicated output pin, we are limited to at most 14 signals (digital pins 0 to 13). To connect N > 14 signals we need a different approach. Instead of N parallel connections (giving each a dedicated output pin) we can use a single pin and send a series of N single-bit values. Each value represents one of the N different signals. This serial signal will be received by an external serial to parallel converter and converted back to the N parallel signals that we need. One simple device that can perform serial to parallel conversion is a shift register.

1.1

Build a bar-graph display interface using a shift register

 Disconnect your Arduino USB cable. Do not connect it again until the instructor has checked your circuit. If your shift register is not properly connected, you will destroy the device!

 Connect a 74HC164 shift register to the Arduino. The

470

inputs can be connected directly to the microcontroller digital pins as follows: → → →

CLK DA and DB CLR

(pin 8) (pins 1 and 2) (pins 1 and 2)

VCC 1

DA

2

D3

Don’t forget to connect 5 V and GND from the microcontroller to the VCC and GND pins (respectively) on the shift register.

microcontroller

D2 D3 D4

470

14

5V

D2

D4

Q0

3

Q1

4

Q2

5

Q3

6

Q4

10

Q5

11

Q6

12

Q7

13

DB 8

9

CLK

CLR 74HC164

GND

GND

470 470 470 470 470 470 470 470

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 Connect the shift register out-

puts to the first eight LEDs of a bar-graph array. The shift register can supply a total of 50 mA of current, or about 6.25 mA per LED. Each LED has a forward voltage drop VF = 2.2 V, so you will have to use currentlimiting resistors of at least 2.8/.00625 = 448 Ω. The closest standard value is is 470 Ω. (Ask the instructor for a network of 10 resistors in a convenient single package, as shown in the diagram.)

 Check again that the shift register and the LED display are correctly oriented! Pin 1 on the shift register is next to the small dot, at the end of the device marked with a semicircular notch. Pin 1 on the LED array is next to the corner that is angled at 45◦ .

, 1 Ask the instructor to check your work.

 When your program is ready, you can reconnect your USB cable. 1 of 2

1.2

Create a program to test the shift register’s operation

1.2

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SERIAL TO PARALLEL CONVERSION

Create a program to test the shift register’s operation

 Write a pair of functions called posPulse(pin) and negPulse(pin).

The function posPulse() should generate a positive pulse on the given pin. (Use digitalWrite() to set pin first to HIGH, and then immediately back to LOW.) The function negPulse() should generate a negative pulse on the given pin. (Use digitalWrite() to set pin first to LOW, and then immediately back to HIGH.)

 In the setup() function, use pinMode() (or DDRD) to configure digital pins 2, 3 and 4 as OUTPUTs. and then use digitalWrite() (or PORTD) to initialise them as follows:

DA DB

signal

pin

initial state

purpose

D CLK CLR

D3 D3 D5

LOW LOW HIGH

data value ‘0’ (a known state) inactive (ready for a rising edge) not asserted (register is not being cleared)

 Still in the setup() function, clear the shift register outputs by generating a negative pulse on CLR.

CLK CLR

74HC164 D

8-stage shift register RESET

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

serial data D (D2) clock CLK (D3) clear CLR (D5) outputs Q0 − Q7

 In the loop() function, test the register’s operation by shifting a single bit through all eight stages: • Set D to ‘1’ (HIGH).

• Shift D into the register (generate a positive pulse on CLK). • Set D to ‘0’ (LOW). • Repeat eight times: – generate a delay for 100 ms. – Shift D into the register (generate a positive pulse on CLK). • generate a delay for 500 ms. The resulting signals will follow this pattern: serial data D (D2) clock CLK (D3) repeat →

← 8 times

, 2 Ask the instructor to check your work.

(If your circuit and program are correct you should see the LEDs light up one at a time.)

 What happens if you disable (comment out) step 3 (‘set D to 0’) in your loop() code? 1.3

Challenges

 (medium) Make the LEDs light up in the opposite order.  (easy) Alternately turn all of the LEDs on, then turn them all off.  (medium) Make the LEDs count in binary. (Remove your delay() and see what happens. Then try the following challenge...)

 (medium-difficult) Turn on LEDs 1, 3, 5 and 7 at full brightness, and LEDs 2, 4, 6 and 8 at half brightness.  (difficult) Flash LEDs 1, 3, 5 and 7 at full brightness, while flashing LEDs 2, 4, 6 and 8 at half brightness.  (difficult) Add another shift register to your circuit. Connect the Q7 output on the first register to the D input on

the second register. You now have a 16-bit shift register. Connect the first two outputs on the second shift register to the remaining two LEDs of the LED bar-graph display. Repeat some of the above challenges using all ten LEDs.

 (medium) Ask the instructor for a 74HC595 shift register, which has additional output enable (OE) and register

clock (RCLK) inputs. Connect these inputs to two additional digital outputs on the microcontroller. Modify your program to correctly operate the 74HC595, testing it with some of the above challenges. 2 of 2

A

Reference Review of digital electronics

voltage 0 V 5V Digital electronics deals with binary signals. A binary signal represents some voltage level LOW HIGH logical information: yes or no, true or false, 1 or 0, and so on. These two binary value 0 1 possible states are represented by voltage levels, nominally 5 V and 0 V, which logic false true can also be written HIGH and LOW, respectively. The precise voltage of a digital signal is often not important. What counts is whether it is above or below some threshold. For example, the popular 74HC devices using 5 V logic generate output voltages ≥ 3.98 V to represent HIGH, and ≤ 0.26 V to represent LOW. They consider any input voltage ≥ 3.1 V to be HIGH and any voltage ≤ 1.35 V to be LOW. (Voltages between these thresholds are undefined. They may be considered HIGH or LOW depending on many unpredictable factors including manufacturing process variations, temperature, etc.) Another common standard uses 3.3 V instead of 5 V. 3.3 V devices are usually not compatible with 5 V logic, and can be damaged if exposed to voltages higher than 3.3 V. The data sheet for a device contains authoritative information such as the voltages it tolerates, and what levels it expects to represent LOW and HIGH.

A.1

Active-high and active-low signals

Every digital signal provides a yes/no answer to some question. When the signal represents ‘yes’ is it active; when it represents ‘no’ it is inactive. For example, some devices only respond to input when they are selected (the entire chip is enabled). These devices have a chip select input. When the ‘chip select’ input is active the device will respond to its other inputs; when ‘chip select’ is inactive the device ignores its other inputs. Either of the two logic levels (HIGH or LOW) can be used signal meaning to represent ‘active’ (and the opposite level used to represent voltage active high active low ‘inactive’). Signals that are active high are considered active LOW inactive (off, ‘no’) active (on, ‘yes’) when their level is HIGH. Signals that are active low are conHIGH active (on, ‘yes’) inactive (off, ‘no’) sidered active when their level is LOW. The active level for a signal is almost always indicated in its name. The two most common conventions are to write active-low signals with a line over their name, or the letter ‘N’ after their name. For example, if a ‘chip select’ signal is active high then it might be called CS; if it is active low then it might be called CS or CSN. Active low signals are sometimes identified in circuit diagrams by drawing a small hollow circle at the point where the signal enters or leaves the device.

A.2

Timing diagrams

Digital signals are displayed graphically in a timing diagram. The horizontal axis is time, increasing towards the right. (a) low

(b) high

(c) either

(d) undefined / don’t care (e)

signal S The vertical axis shows signal voltages. Each signal’s state is displayed as a voltage level, LOW (a) or HIGH (b). To show that a well-defined signal is present, without specifying its level, it can be drawn with both levels simultaneously (c). To show that a signal is undefined (for outputs) or ‘don’t care’ (for inputs) it can be drawn with both levels and either shading (d) or crosses (e).

A.3

Rising and falling edges

rising falling Digital signals change state. A change from one state to the opposite state edge edge is called a transition. The signal voltage will either rise abruptly from LOW to ↓ ↓ HIGH, or fall abruptly from HIGH to LOW. In the corresponding voltage waveform, clock C this abrupt change is called an edge and is usually qualified with its direction. high low low A rising edge happens during a transition from LOW to HIGH, and a falling edge during a transition from HIGH to LOW. Edges often represent significant instants in time. A regular periodic signal can be used as a clock, with activities synchronised to the rising or falling edge of the signal (or both). Clock inputs on devices are often identified in circuit diagrams by drawing a small triangle just inside the device outline. The edge of an irregular signal can indicate that an asynchronous event has occurred. When the edge occurs, we say the signal is asserted to indicate the event is happening. For example, many devices have a RESET input. When RESET is inactive, the device performs its normal function. When the RESET signal is asserted (changes from inactive to active) the device resets by placing itself in a specified, default state.

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Devices that respond to the edges of a signal are called edge triggered. They can be positive edge triggered (responding to the rising edge) or negative edge triggered (responding to the falling edge). A trigger edge is sometimes emphasised in timing diagrams by drawing an arrow on it.

A.4

rising-edge triggered C falling-edge triggered C

Some standard logic gates

The common logic operators are augmented with versions having negated outputs (e.g., nand, nor, and xnor). A

BA 0 0 1 1

0 1 0 1

A.5

OUT

A

OUT

A B

OUT

A B

OUT

A B

OUT

A B

OUT

buffer

not

and

nand

or

xor

0 1

1 0

0 0 0 1

1 1 1 0

0 1 1 1

0 1 1 0

Tri-state outputs

A/B output select OUTPUTS Tri-state (or 3-state) logic allows multiple output signals to share a single electrical connection. They are used whenever multiple outputs need to be condevice A nected to a single input. Tri-state outputs can have three states: the usual ENABLE OUTPUT LOW and HIGH, plus a third high impedance (or high-Z) state which disconnects the output from the internal circuitry of the device. When an output is in the inverter (logical ‘not’) high-Z state, the voltage level of the signal that it is connected to can be set device B by some other output that shares the same connection. ENABLE OUTPUT In timing diagrams, a tri-state signal that is disabled (high-impedance) is (A/B) often drawn as a line half way between LOW and HIGH. For example, two devices, A and B, have their tri-state OUTPUTs connected to form a single combined OUTPUTS signal. Each device has an ENABLE input. output select A/B When the ENABLE input is active, the device’s OUTPUT will provide a LOW or A device A OUTPUT HIGH voltage level. When the ENABLE input is inactive, the device’s OUTPUT B device B OUTPUT will be in a high-impedance state that allows another device to determine A B combined OUTPUTS the state of the combined OUTPUTS. An inverter between the two ENABLE ensures only one of the devices is enabled at a time. In the first half of the timing diagram device A is enabled and it determines the state of the combined OUTPUTS; device B is disabled and its output has no effect on the circuit. In the second half device B is enabled and it determines the state of the combined OUTPUTS; device A is disabled and its output has no effect on the circuit.

A.6

A comprehensive example device: the D-type flip-flop

positive-edge-triggered D-type flip-flop with asynchronous clear and 3-state outputs

A D-type flip-flop is an edge-triggered device that copies the state of its input pin D to the output pin Q whenever it is triggered by the rising edge of its clock input CLK. D-type flip-flops often have a ‘clear’ (reset) input CLR that sets Q to LOW independently of D and CLK. Some have an output enable OE that isolates the output pin Q from the internal circuitry when inactive. Some have a complementary output Q that is always the inverse of Q. An example of an edge-triggered D-type flip-flop with active-low clear and output enable pins is shown on the right. A timing diagram illustrating its operation is shown below. A

B

C

D

E

OE D

Q CLK Q CLR

F

G

clock CLK data D output Q complement Q clear CLR output enable OE At A, B and C, the rising edge of CLK triggers the flip-flop to copy D to Q. At D, CLR becomes active (low) and resets the device, forcing the output Q low. The output remains low, regardless of D and CLK, until CLR becomes inactive at E. At F, D can be copied to Q again as usual. At G, OE becomes inactive (high) causing the outputs to be isolated from the internal circuitry. 2

A.7

Fan-out

The fan-out of an output pin is the maximum number of inputs to which it can be safely connected. One output can be connected to one or more inputs on other devices. When the output is high it sources (provides) current and the inputs sink current. When the output is low it sinks current and the inputs must source current. Each output has a maximum current it can source or sink, and each input has a maximum current it will sink or source when driven. For reliable operation (voltage levels having welldefined logical meaning) an output must not source or sink more current than its rated maximum. (These maximums are specified in the data sheet for the device.) For an output to safely drive N inputs, two conditions must therefore be satisfied:

DN HIGH

QH

D1

IH

DN IL

QL

• output HIGH: the maximum source current of the output must be larger than the sum of the maximum sink currents of all the inputs to which it is connected; and

LOW

IH >=

N X

D1

sink(Di )

i=1

• output LOW: the maximum sink current of the output must be smaller than the sum of the maximum source currents of all the inputs to which it is connected. IL <= For a given circuit configuration, the maximum value of N for which the above constraints are satisfied is called the fan-out for the output.

A.8

source(Di )

i=1

Shift registers CLK

A shift register is a two-input, N -output device. A single serial data input D is sampled every time a rising edge is seen on the clock input CLK. The last N values of D that were sampled are stored and made available on the N outputs Q0 to QN−1 . Depending on the shift register, additional inputs and outputs might be available. Some examples include:

L|H|L|H|L|H|L|H|L|H|L|H|L|H|L|H|L|H

D 0 0 1 0 0 1 1 0 0 Q1 Q2 Q3 Q4

OE (input) is an output enable. Whenever OE is active, the outputs are enabled and generate LOW or HIGH voltages to reflect the state of the stored bit. When OE is inactive, the outputs are disabled and behave as if they are not electrically connected to a voltage source.

0 0 0 0

0 0 0 0

1 0 0 0

0 1 0 0

0 0 1 0

1 0 0 1

1 1 0 0

0 1 1 0

0 0 1 1

(× = ‘don’t care’)

L|H|L|H|L|H|L|H|LLL|H|LLL|H RCLK LLLLLLLLL|H|LLL|H|LL CLK

RCLK (input) is the output register clock. If this input is available then the values of bi are not copied to the output pins Qi when CLK rises. The shift register works as normal, shifting the stored bits bi one stage each clock cycle, but their values are only copied to the outputs Qi when RCLK rises. This provides buffered output, and allows a long value to be shifted into the register without disturbing the outputs until a rising RCLK causes them to be updated.

D 0 1 0 0 × 1 × 1 Q1 Q2 Q3 Q4 Q04

Q0N (output) provides an unbuffered copy of QN that can be used to cascade two shift registers together, effectively making a shift register with twice as many bits. A.8.1

N X

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 0 1 0 0

0 0 1 0 1

1 0 0 1 1

1 0 0 1 0

The 74HC164 shift register

The 74HC164 is a simple shift register, supporting clock frequencies up to 78 MHz. It has four inputs: logical

DB serial data input

physical

14

VCC

CLK serial data clock (positive-edge triggered)

1

DA

Q0

3

Q1

4

2

CLR asynchronous clear (active low)

Q2

5

74HC164

Q3

6

CLK

Q4

10

Q5

11

Q6

12

DB

The 74HC164 has eight outputs:

8

Q0 –Q7 eight parallel data outputs

9

CLR

DA

1

14

VCC

DB

2

13

Q7

Q0

3

12

Q6

Q1

4

11

Q5

Q2

5

10

Q4

Q3

6

9

CLR

74HC164

DA serial data input

13 The two data inputs, DA and DB are ‘and’ed together internally Q7 GND 8 GND 7 CLK before becoming the input to the first shift register stage. Both 7 must therefore be HIGH for a ‘1’ to be shifted into the register. Multiple 74HC164s can be cascaded to form an arbitrarily-long shift register, by connecting the Q7 output of each device to the D input of the next and running them all from the same clock.

3

A.8.2

The 74HC595 shift register

The 74HC595 is a typical (and popular) shift register, supporting clock frequencies up to 20 MHz. It has five inputs: logical

CLK serial data clock (positive-edge triggered)

14

RCLK output register clock (positive-edge triggered)

QB

VCC

16

QB

1

2

QC

QA

15

QC

2

3

QD

D

14

QD

3

4

QE

OE

13

QE

4

5

QF

RCLK

12

QF

5

6

QG

CLK

11

QG

6

7

QH

CLR

10

QH

7

8

GND

CLK

10

CLR

OE output enable (active low)

74HC595 12

RCLK

The 74HC595 has nine outputs: QA –QH eight parallel data outputs Q0H

QA

1

D

11

CLR asynchronous clear (active low)

physical 15

13

OE

serial data output (can be used to cascade several shift registers together)

QH’

74HC595

D serial data input

QH’

9

9

The device functions as a normal shift register, except that the eight shift register stages are not connected directly to the outputs. Instead they are connected to an internal 8-bit parallel output register, with its own clock input. The bits stored in the shift register itself are clocked into the output register on the rising edge of the RCLK input. 74HC595

low = set all to 0

D CLK

input data clock

8-stage shift register

CLR QH’ RCLK

OE

CLR CLK D

74HC595

8-stage shift register QH’

input data

8-bit storage register

RCLK storage register clock (copy shift register)

3-state outputs

OE

8-bit storage register

3-state outputs

high = disabled low = enabled QA QB QC QD QE QF QG QH

QA QB QC QD QE QF QG QH

The device can be operated with CLK and RCLK connected together, which causes the shift register to be copied to the outputs at the same time as D is copied into the first stage of the shift register. However, this introduces an additional clock cycle’s delay between the data being sampled at D and it appearing at the first output bit. When the OE input is high, the outputs are high-impedance. The outputs can be connected to other tri-state outputs, from other devices, provided only one of the devices has its output enabled at any given time.

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