Chapter 10
Memory & Simple I/O Interfacing Expected Outcomes Explain the importance of tri-state devices in microprocessor system Distinguish basic type of semiconductor memory and their applications Relate the address and data bus for various memories Describe I/O interfacing concept such as I/O driver and memory mapped Relate the role of latch and buffer in interfacing with simple I/O devices
NMKNYFKEEUMP
Tri-state Devices Any devices connected to a microprocessor should configure in tristate This is because only one device can communicate with the processor at one time leaving other devices at high impedance Devices with tristate outputs have an enable input such as OE, CS, E, etc With this configuration, there will not be any devices fighting for control of common wire which may cause damaging to current flow Common devices connected to mP Address decoder Memory (ROM/RAM) Input devices such as keyboard, mouse, switch etc Output devices such as printer, monitor, LED, LCD NMKNYFKEEUMP
Tri-state Devices Lower address
Upper address
RAM
ROM
CS
CS
mP
CS
Chip selector Address Decoder
NMKNYFKEEUMP
LED CS
Memory
NMKNYFKEEUMP
Memory Memory system is used to store data and instruction Type of memory ROM (Read Only Memory) Nonvolatile – data remains even the power is off Normally used to store vectors, self-test routine, monitor program, common subroutine and etc Special device is required to store program in ROM
RAM (Random Access Memory) Volatile type as data are lost as the power is off Temporary storage and normally used for operation and application system
NMKNYFKEEUMP
ROM Programmable Maskable ROM Very cheap and normally is programmed in factory for mass production One-time written and widely used in game cassette Programmable ROM (PROM) One-time written and can be programmed by using PROM programmer One-time PROM (OTPROM) Cheap version of PROM with plastic packed
NMKNYFKEEUMP
ROM Flash Memory Like EEPROM, but erasing process involves block-by-block Common in digital camera & MP3
PROM
less expensive ROM
EEPROM
OTPROM EPROM
NMKNYFKEEUMP
more expensive
EPROM Common industrial EPROM 2716 2 kbyte (2048 x 8 bits) 2732 4 kbyte (4096 x 8 bits) 2764 8 kbyte (8192 x 8 bits) 27128 16 kbytes (16384 x 8 bits) 27256 32 kbytes (32768 x 8 bits) Common industrial EEPROM 2816 2 kbyte (2048 x 8 bits) 2864 8 kbyte (8192 x 8 bits)
+5V
Address bus
A0 - An
D0 - D7
OE* CS* Vpp GND
NMKNYFKEEUMP
Data bus
EPROM Part No
Capacity
Org
Access
Pins
Vpp
2716
16K
2Kx8
450ns
24
25V
2732
32K
4Kx8
450ns
24
25V
27C32-1
32K
4Kx8
450ns
24
25V CMOS
2764-20
64K
8Kx8
200ns
28
21V
27C64-12
64K
8Kx8
120ns
28
12.5V CMOS
27128-25
128K
16Kx8
250ns
28
21V
27C256-15
256K
32Kx8
150ns
28
12.5V CMOS
27C512-15
512K
6Kx8
150ns
28
12.5V CMOS
27C010-15
1024K
128Kx8
150ns
32
12.5V CMOS
27C020-15
2048K
256Kx8
150ns
32
12.5V CMOS
27C040-15
4096K
512Kx8
150ns
32
12.5V CMOS
NMKNYFKEEUMP
EEPROM & Flash Chip Some common EEPROM Part No
Capacity
Org
Speed
Pins
Vpp
2816A-25
16K
2Kx8
250ns
24
5V
2864A
64K
8Kx8
250ns
28
5V
28C64A-25
64K
8Kx8
250ns
28
5V CMOS
28C256-15
256K
32Kx8
150ns
28
5V
Some common Flash Chips Part No
Capacity
Org
Speed
Pins
Vpp
28F256-20
256K
32Kx8
200ns
32
12V CMOS
28F010-15
1024K
128Kx8
150ns
32
12V CMOS
28F020-15
2048K
256Kx8
150ns
32
12V CMOS
NMKNYFKEEUMP
EPROM Pin Function A0-An (Address Bus) Address bus directly connected to lower address of microprocessor D0-Dn (Data Bus) Data bus directly connected to data bus CS* (Chip Select) To activate EPROM and connected to address decoder OE* (Output Enable) ROM place data into data bus NMKNYFKEEUMP
EPROM Pin Function Vpp Used by EPROM programmer to change bit in the chip Place into high when it is not used CS*
OE*
Functions
1
0
IC disable with minimum power consumption
1
1
IC disable with minimum power consumption
0
0
Read mode; data are placed on data bus
0
1
Wait state mode; data are placed on the bus when OE* is activated
NMKNYFKEEUMP
EPROM Memory Chip Examples of Parallel EPROMs 2716 1 2 3 4 5 6 7 8 9 10 11 12 13 14
A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND
2732
2764
27128
27256
27512
A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND
Vpp A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND
Vpp A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND
Vpp A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND
A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND
2716 28 27 26 25 24 23 22 21 20 19 18 17 16 15
NMKNYFKEEUMP
Vcc A8 A9 A11 OE* A10 CE D7 D6 D5 D4 D3
2732
2764
27128
27256
27512
Vcc A8 A9 A11 OE* A10 CE D7 D6 D5 D4 D3
Vcc PGM N.C A8 A9 A11 OE* A10 CE D7 D6 D5 D4 D3
Vcc PGM A13 A8 A9 A11 OE* A10 CE D7 D6 D5 D4 D3
Vcc A14 A13 A8 A9 A11 OE* A10 CE D7 D6 D5 D4 D3
Vcc A14 A13 A8 A9 A11 OE*/Vpp
A10 CE D7 D6 D5 D4 D3
RAM Two basic types of RAM Static RAM (SRAM) Easy to be used and requires an internal flip-flop to store each bit Need 4 – 6 transistor for each FF and suitable for small system 4 times compact than SRAM with the same size Normally used in personal computer
Dynamic RAM (DRAM) Cheaper as dynamic RAM uses a single transistor that acts like a charged capacitor to store each bit Since the charge leaks, a DRAM must use refresh circuit to recharge the capacitor periodically (typically every 2 ms) NMKNYFKEEUMP
RAM & NVRAM Performance difference DRAM contain more data per chip size SRAM is faster and simpler NV-RAM (Non-volatile RAM) is introduced to allow the CPU to read and write to it and not lost the content even the power is turned off To retain the content, the NVRAM chip internally Uses extremely power efficient – CMOS Uses an internal lithium battery as backup energy Uses intelligent control circuitry to monitor Vcc pin and activates internal power if needed Thus the NV-RAM is expensive because it must provide the facilities in a single IC NMKNYFKEEUMP
SRAM & DRAM Examples of SRAM & DRAM Part No
Capacity
Org
Speed
Pins
Vpp
6116P-1
16K
2Kx8
100ns
24
CMOS
6116LP-3
16K
2Kx8
150ns
24
CMOS
6264P-10
64K
2Kx8
100ns
28
CMOS
62256LP-10
256K
32Kx8
100ns
28
Low Power CMOS
62256LP-12
256K
32Kx8
120ns
28
Low Power CMOS
Part No
Capacity
Org
Speed
Pins
4164-15
64K
64Kx1
150ns
16
41256-15
256K
256Kx1
150ns
16
511000P-8
1M
1Mx1
80ns
18
NMKNYFKEEUMP
NVRAM NV-RAM from Dallas Semiconductor Part No
Capacity
Org
Speed
Pins
DS1220Y-150
16K
2Kx8
150ns
26
DS1225AB-150
64K
8Kx8
150ns
28
DS1230Y-85
256K
32Kx8
85ns
28
NMKNYFKEEUMP
RAM Common industrial RAM 6116 2 kbyte (2048 x 8 bits) 6164/6264 8 kbyte (8192 x 8 bits) 43256/6625 32 kbytes (32768 x 8 bits)
NMKNYFKEEUMP
+5V
Address bus
A0 - An
D0 - D7
OE* CS* WE* GND
Data bus
RAM A0-An (Address Bus) - Address bus directly connected to lower address of microprocessor D0-Dn (Data Bus) - Data bus directly connected to data bus CS* (Chip Select) - To activate EPROM and connected to address decoder
OE* (Output Enable) - RAM places data into data bus WE* (Write Enable) - RAM stores data into cell
NMKNYFKEEUMP
RAM The role of CS*, OE* and WE* CS*
OE*
WE*
Functions
1
X
X
IC disable with minimum power consumption
0
0
0
Undefined
0
0
1
Read mode; data are placed on data bus
0
1
0
Write mode; data are latched
0
1
1
Wait state mode
NMKNYFKEEUMP
2764 vs 6264 2764
6264
Vpp
1
28
Vcc
N.C
1
28
Vcc
A12
2
27
PGM*
A12
2
27
WE*
A7
3
26
N.C
A7
3
26
CS2
A6
4
25
A8
A6
4
25
A8
A5
5
24
A9
A5
5
24
A9
A4
6
23
A11
A4
6
23
A11
A3
22
OE*
A3
OE*
21
A10
A2
7 8
22
A2
7 8
21
A10
A1
9
20
CE*
A1
9
20
CS1*
19
D7
18
D6
A0
19
D7
D0
10 11
A0
18
D6
D0
10 11
D1
12
17
D5
D1
12
17
D5
D2
13
16
D4
D2
13
16
D4
GND
14
15
D3
GND
14
15
D3
NMKNYFKEEUMP
Access Time The performance of memory chips normally are based on access time Access time (tac) is defined as time taken for the memory to place data onto the data bus as the read signal is received Address
valid address
CS*
Data
valid data tac
NMKNYFKEEUMP
Simple I/O Devices
NMKNYFKEEUMP
Input Devices Most input devices do not possess the tristate configuration Normally they are connected to other tristate devices such as buffer to ensure proper interface with mP Common input devices Switches (reset, SPST, SPDT etc) Keypad Sensors X1 X2 X3 X4
NMKNYFKEEUMP
1
2
3
A
4
5
6
B
7
8
9
C
*
0
#
D
Y1 Y2 Y3 Y4
Buffer Buffer is a circuit that allows any logics onto the data bus 74LS244 unidirectional tri-state buffer If OE=0, input is allowed to pass through If OE=1, output is placed in high impedance 74LS245 bidirectional buffer A.k.a transceiver Data direction is determined by DIR If DIR=0, data movement is from A to B If DIR=1, data movement is from B to A
NMKNYFKEEUMP
Buffer 74LS244 2 4 6 8 11 13 15 17
74LS245 18 Q0 16 Q1 14 Q2 12 Q3 9 Q4 7 Q5 5 Q6 3 Q7
D0 D1 D2 D3 D4 D5 D6 D7
OE1 OE2 1
2 3 4 5 6 7 8 9
B0 B1 B2 B3 B4 B5 B6 B7
A0 A1 A2 A3 A4 A5 A6 A7 DIR EN 1
19
NMKNYFKEEUMP
19
18 17 16 15 14 13 12 11
Simple Input Interface +5V
Simple inputs connection with a buffer Enable pins (OE1* & OE2*) will activate the buffer and normally are connected to address decoder
1k
D8-D15
Q7
D7
Q6
D6
Q5
D5
Q4
D4
Q3 74244 D3 Q2
D2
Q1
D1
Q0
D0
OE1 OE2
NMKNYFKEEUMP
1k 1k 1k 1k 1k 1k 1k
Keypad Encoder When a keypad is used in a system, a keypad encoder (74922) is required to facilitate the program 74C922
1
X1 X2 X3 X4
2
3
A
4
5
6
B
7
8
9
C
*
0
#
D
Y1 Y2 Y3 Y4
2 3 4 5 6 7 8 9
D0 D1 D2 D3 DA
X1 X2 X3 X4 Y1 Y2 Y3 Y4 LE 20
NMKNYFKEEUMP
OE 1
12 13 14 15 16
To mP
Output Devices Like input devices, output devices do not possess the tristate configuration They are connected to other tristate devices such as latch for proper interface with processor Common output devices Light Emitting Diode (LED) Seven Segment Display Dot Matrix
C1 C2 C3 C4 C5 C6 C7 C8
R1 R2
a
R3 R4
f
g
b
R5 R6 R7
e
d
c dp
NMKNYFKEEUMP
R8
LED LED is the most common output device used in microprocessorbased system due its simplicity & cost +5V
'1'
+5V
'0' 330R
330R
'1'
'0' 330R
330R
NMKNYFKEEUMP
7-Segment Display There two type configurations Common Anode Common Cathode
a b c d e f g dp
+5V
LATCH
LATCH
Common Cathode
Common Anode
NMKNYFKEEUMP
7-Segment Display Common Cathode Common Anode
a f
e
g
d
b
c dp
NMKNYFKEEUMP
7-Segment Display a
Common Cathode
f
e
g
d
b
c dp
a
b
c
d
e
f
g
a
b
c
d
e
f
g
0
1
1
1
1
1
1
0
8
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
9
1
1
1
0
0
1
1
2
1
1
0
1
1
0
1
A
1
1
1
0
1
1
1
3
1
1
1
1
0
0
1
B
0
0
1
1
1
1
1
4
0
1
1
1
0
0
1
C
1
0
0
1
1
1
0
5
1
0
1
1
0
1
1
D
0
1
1
1
1
0
1
6
1
0
1
1
1
1
1
E
1
0
0
1
1
1
1
7
1
1
1
0
0
0
0
F
1
0
0
0
1
1
1
NMKNYFKEEUMP
Latch Latch is a circuit that capture value at the input 74LS373 transparent latch During LE=1, Q=D During LE=0, Q hold D during negative edge Another version is 74LS573 where the difference is in pin configuration 74LS374 edge triggering During positive transition at CP, data is transferred from D to Q Another version is 74LS574 where the difference is in pin configuration
NMKNYFKEEUMP
Latch 74LS373 3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
74LS374
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE 11
OE 1
2 5 6 9 12 15 16 19
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
74LS573
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP 11
OE 1
NMKNYFKEEUMP
2 5 6 9 12 15 16 19
2 3 4 5 6 7 8 9
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE 20
OE 1
12 13 14 15 16 17 18 19
Dot Matrix A multi-purpose output display, dot matrix is another common output device C1 C2 C3 C4 C5 C6 C7 C8
C1 R1 R1
R2
R2
R3 R4
R3
R5
R4
R6
R5
R7
R6
R8
R7 R8
NMKNYFKEEUMP
Self-Test Determine the number of address pins and memory capacity of the following EPROM Part No
Capacity (bytes)
TMS27C64 HD2716 NM27C128 62256LP-10 27C010-15 27C040-15 27512-25
NMKNYFKEEUMP
Address Pins
Self-Test Exercise For ROM chip 27128, find the number of data and address pins. In your opinion what is the minimum pin configuration of the chip Exercise Discuss the number of pins for addresses in (i) 2 kbytes RAM (ii) 512 bytes of RAM Exercise Explain the difference between EEPROM and flash memory Exercise Which memory is used as cache memory in the PC?
NMKNYFKEEUMP
Self-Test Exercise Explain the role of OE*, CS*, WE* pins in RAM Exercise Why do we need to use latch instead of connecting the output device (such as 7-segment display) directly to the CPU? Exercise What is access time for a memory? Briefly describe the important of fast access time in a microprocessor system by giving an example
NMKNYFKEEUMP
