Serial Interfacing

Serial Interfacing Expected Outcomes ... Some examples of the ICs that provide the EIA-232 line driver are MAX 233, MAX 232 , MC145407 or a pair of MC...

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Chapter 13

Serial Interfacing Expected Outcomes Explain the fundamental idea of operation of serial interface List and describe type of serial interface Identify the serial interface characteristic such as data framing and baud rate Explain and describe the role line driver in serial interface Write a program using serial interface

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Introduction Computers transfer data in two ways Parallel Serial Parallel data transfers often 8 or more lines are used to transfer data to a device that is only a few feet away such as printers and hard disks Parallel requires a short amount of time to transfer data However, the distance of the devices are limited and impractical to be used in a long distance The parallel is complex to be designed and prone to error In serial method, the data is sent one bit at a time NMKNYFKEEUMP

Parallel vs Serial Computers transfer data in two ways Parallel Serial

Transmitter

Receiver

Serial Communication

Transmitter

Parallel Communication

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Receiver

Serial Communication Serial data communication uses two methods Asynchronous Synchronous The synchronous transfers a block of data (characters) at a time, thus requiring the transmitter and receiver to have the same clock system The asynchronous transfers a single byte at a time For a small system, normally asynchronous method is preferred as the design is simple and cheap Specialized chips are designed for both method: UART (Universal Asynchronous Receiver and Transmitter) and USART M68000 family peripheral – MC68681 DUART M6800 family peripheral - MC6850 ACIA NMKNYFKEEUMP

UART Some of the possible connections RxClk

TxClk

RxD P

TxD

UART TxD

RxD

TxClk

RxClk

RxClk

TxClk

P

UART

P

UART

modem

modem

UART

PSTN

TxClk

RxClk

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P

DUART 68681 The MC68681 (dual universal asynchronous receiver/transmitter) is part of M68000 peripheral using asynchronous bus structure Features 2 independent full-duplex asynchronous channels Maximum data transfer rate up to 1 MB/s Programmable data format Programmable channel mode Independent programmable baud rate Versatile interrupt system Multi-function 16-bit programmable counter/timer Multi-function 8-bit output port and etc…

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ACIA 6850 Alternatively, M6800 family peripheral such as ACIA 6850 can be used in serial transmission Asynchronous Communication Interface Adapter (ACIA 6850) is widely used due to cost and simplicity Features Data lines (D0-D7) Chip selects (CS0,CS1 and CS2*) Enable (E) Read and Write (R/W*) Register Select (RS) Received Data (RxD) and Transmit Data (TxD) Transmit Clock (TxClk) and Receive Clock (RxClk) Modem Control Line (CTS*, RTS*, DCD*)

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Data Framing Before transmission each character must be framed Data framing for asynchronous method 1 start bit Always “0” to indicate the beginning of character

5-8 bits data It begins with LSB

1 parity bit (optional) Can be odd or even parity depending on the programmer

1 or more stop bits Always “1” to indicate the end of character Start Bit

Parity Bit

5 - 8 bits data

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Stop Bits

ACIA 6850 Internal architecture of ACIA 6850

IRQ

Status Register (SR)

Receive Data Register (RDR)

D7-D0 RS

Received Shift Register Control Unit

E R/W CS0 CS1 CS2

RTS CTS DCD

RxD

Received Data

TxD

Transmit Data

Transmit Shift Register

Transmit Data Register (TDR)

Control Register (CR)

TxClk RxClk

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From Clock Generator

ACIA 6850 Baud rate generator circuit : Baud rate generator chips such as MC14411or oscillator circuit 68000

6850

A1

RS TxD RxD

A2-A23

Address Decoder

CS2 CTS DCD

VPA* R/W* E

R/W* E

UDS*

CS1

VMA*

CS2

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TxClk RxClk Baud Rate Generator

Registers There are 4 registers Control Register (CR) Status Register (SR) Transmit Data Register (TDR) Receive Data Register (RDR) RS

R/W

Name Register

0

0

CR

Control Register

0

1

SR

Status register

1

0

TDR

Transmit Data Register

1

1

RDR

Receive Data Register

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Registers The address register depends on Address decoder UDS*/LDS* N A1 LDS*

RS CS1

N+2

UDS*

RS CS1

N+1

TDR/RDR

N+3

N+4

N+5

N+6

N+7

N A1

CR/SR

N+2

CR/SR

N+1

TDR/RDR

N+3

N+4

N+5

N+6

N+7

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Control Register The control register (CR) controls the function of the receiver, transmitter, interrupt enables, and the Request-to-Send peripheral/modem control output

CR7 Receive Interrupt Enable Bit Transmitter Control Bits

CR6

CR5

CR4

CR3

CR2

CR1

Data Format (Data size, stop bits, parity) 000 - 7 bit data, 2 stop bits, even 001 - 7 bit data, 2 stop bits, odd 010 - 7 bit data, 1 stop bits, even 011 - 7 bit data, 1 stop bits, odd 100 - 8 bit data, 2 stop bits, none 101 - 8 bit data, 1 stop bits, none 110 - 8 bit data, 1 stop bits, even 111 - 8 bit data, 1 stop bits, odd

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CR0

Counter Divide Select Bits 00 - Divide 1 01 - Divide 16 10 - Divide 64 11 - Master RESET

Status Register Information on the status of ACIA is available by reading the Status Register (SR) SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

IRQ

PE

OVRN

FE

CTS

DCD

TDRE

RDRF

Interrupt Request Parity Error Overrun Error Framing Error

Receive Data register Full Transmit Data Register Empty Data Carrier Detect Clear to Send

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Programming ACIA 6850 ACIA must be initialize in order to operate properly Four parameter must be set between transmitter and receiver Data rate Number of bits Type of parity Number of stop bits

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Programming ACIA 6850 Example: Write a routine to initialize ACIA with the following characteristic; 8 bits, 1 stop bit, no parity. Assume clock frequency is 153.6 kHz INIT MOVE.B MOVE.B MOVE.W LOOP SUBQ.W BNE RTS

#3,ACIACR #$15,ACIACR #$400,D0 #1,D0 LOOP

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;RESET ;Set CR ;Delay

Programming ACIA 6850 In order to transmit or receive data, TDRE and RDRF must be monitored If TDR is empty, TDRE is set, allowing new data to be transmitted Similarly, if RDR is full, RD is set and a new data must be read

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TDRE=1?

Yes

Write a byte to TDR

RDRF=1?

Yes Read a byte from RDR

Programming ACIA 6850 Example: Write a routine to send a character „A‟ continuously SCAN BTST.B #1,ACIASR BEQ SCAN MOVE.B #’A’,ACIADR BRA SCAN RTS

;TDRE = 1? ;No, scan again ;Load ‘A’ into DR ;Repeat sending

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Programming ACIA 6850 Example: Read a byte from Data Receive register and store in D0 SCAN BTST.B #0,ACIASR BEQ SCAN MOVE.B ACIADR,D0 RTS

; Read Status Register ; RDRF=0,scan again ; Store a byte in D0

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Line Driver The 6850 provides two pins (TxD and RxD) to be used specifically to transfer and receive data serially Since the pins are TTL compatible, they require line driver to allow data to be transmitted at a longer distance The most common line drivers are RS-232, RS422 and RS423 However, RS-232 (EIA 232) is widely used as it s the simplest and the cheapest line driver Some examples of the ICs that provide the EIA-232 line driver are MAX 233, MAX 232 , MC145407 or a pair of MC1488/MC1489

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EIA-232 Widely used for serial interface standard Logic “1” is represented by -30 to -25 V and logic “0” is +3 to +25 V allowing the communication to be up to 10 meter There are two type of RS232 connectors; DB-25 and DB-9 Pin 1 2 3 4 5

Description Data Carrier Detect (DCD) Received Data (RxD) Transmitted Data (TxD) Data Terminal Ready (DTR) Signal Ground (GND) NMKNYFKEEUMP

Pin 6 7 8 9

Description Data Set Ready (DSR*) Request To Send (RTS*) Clear To Send (CTS*) Ring Indicator (RI)

EIA-232 MAX232 internal architecture +5V 1F 1

16

2 6

1F 3 4

1F

6850

MAX232 11

11

RxD 10

12

TxD

1F 11 12 10 9

TTL side

5 T1in R1out T2in R2in

DB-9 14 2 13

T1out R1in T2out R2in

14 13 7 8

RS232 side

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3 5

Baud Rate To ensure a proper communication, the baud rate of the system must match the baud rate of the PC‟s COM port The baud rate for the system depends on baud rate generator (TxClk and RxClk)

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Standard baud rate 110 150 300 600 1200 2400 4800 9600 19200 28800

Self-Test Exercise Explain the advantage of using serial transmission compare to parallel transmission Exercise Describe the important of using line driver such as EIA232 or RS422 Exercise What is the difference between MAX232 and MAX233? Exercise State and elaborate the pin requirement for asynchronous transmission NMKNYFKEEUMP

Self-Test Exercise Briefly explain the procedure for sending a byte of data using ACIA 6850 Exercise State and explain bits (TDRE and RDRF) in status register Exercise What is the difference between synchronous and asynchronous transmission Exercise A 1024 x 512 x 16-grey-level image is to be transmitted to a printer using serial communication at the rate of 19.6 kbps. The data format is one start bit, 8 data bit and one stop bit. How long does it takes to transmit the image? NMKNYFKEEUMP